Abstract: A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: A method according to an embodiment of a filter design tool is provided and includes receiving filter parameters for an analog filter through a user interface, where the filter parameters include an optimization parameter related to an application requirement of the analog filter, optimizing the filter for the optimization parameter, calculating a design output based on the optimized filter, and displaying the design output on the user interface. The method can further include receiving viewing parameters that specify the design output to be displayed. In various embodiments, the user interface includes an input area, a viewing area and a window area in one or more pages, where the input area is contiguous to the viewing area in at least one page. The filter parameters can be entered in the input area and the design output is calculated and displayed in the contiguous viewing area substantially immediately.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: Electrical networks are formed to produce an approximation of at least one desired performance characteristic, based on the recognition that fabrication variations introduce slight differences in electronic sub-networks which were intended to be identical. These fabrication differences are turned to an advantage by providing a pool of sub-networks, and then selectively connecting particular combinations of these sub-networks to implement networks that approximate the desired performance characteristics. The sub-networks are of like kind (e.g., resistors) and have a like measure.

Abstract: Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (Vos) error for a “main” differential pair. One trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming Vos error that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim Vos error due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim Vos error that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.

Abstract: An op amp includes a pair of buffer amplifiers interposed between the current switch and the output transistors in an output stage based on the Monticelli architecture. The buffer amps buffer the output transistors' gate capacitances, thereby allowing the output transistors to be nearly any desired size without adversely affecting the op amp's dynamic performance. This enables the op amp's compensation capacitors to set the amplifier's bandwidth, and allows the secondary pole to be at a higher frequency. The buffer amplifiers can also provide gain which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. In addition, the buffer amplifiers can be used to provide voltage level translation between the current switch and output transistors, which can provide additional headroom for the op amp's gain stage.

Abstract: A structure and a method are provided to convert the value of a digital word to an analog signal representing that value, using a small and simple charge divide-by-four circuit with one op amp. The D/A converter thus provided greatly reduces the effects of capacitor mismatch. The D/A converter processes one bit pair at a time and stores a corresponding charge. This charge is divided by four prior to processing the next bit pair. In one embodiment, the D/A converter has one operational amplifier, two capacitors, and seven switches. In another embodiment, the same number of elements are used in a different configuration, which allows an offset correction to be performed. In yet another embodiment, the D/A converter has one op amp, four capacitors, and eleven switches, which allows both offset voltage and gain compensation correction.

Abstract: An amplifier circuit with improved turn-on transient operation includes a differential amplifier and a selectively variable reference generator for controlling the amplifier output during circuit turn-on. The amplifier is biased by a single power supply and its differential inputs are driven by a reference voltage from the reference generator and a single-ended input signal. Following circuit turn-on, the selectively variable reference voltage, generated by charging the bypass capacitor with a constant current source, charges in a linear manner from ground potential toward its final value of, typically, half of the power supply voltage. This allows improved turn-on transient operation to be realized, e.g. reduced "pops" and "clicks" upon circuit turn-on, while giving the user increased flexibility in selecting the sizes of the reference voltage bypass capacitor and the input signal coupling capacitor.