Patents by Inventor Arthur J. Pitera

Arthur J. Pitera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240390896
    Abstract: An interposer for a flow cell comprises a base layer having a first surface and a second surface opposite the first surface. The base layer comprises black polyethylene terephthalate (PET). A first adhesive layer is disposed on the first surface of the base layer. The first adhesive layer comprises methyl acrylic adhesive. A second adhesive layer is disposed on the second surface of the base layer. The second adhesive layer comprises methyl acrylic adhesive. A plurality of microfluidic channels extends through each of the base layer, the first adhesive layer, and the second adhesive layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: ILLUMINA, Inc.
    Inventors: Maxwell Zimmerley, LiangLiang Qiang, M. Shane Bowen, Steven H. Modiano, Dajun Yuan, Randall Smith, Arthur J. Pitera, Hai Quang Tran, Gerald Kreindl
  • Patent number: 12083514
    Abstract: An interposer for a flow cell comprises a base layer having a first surface and a second surface opposite the first surface. The base layer comprises black polyethylene terephthalate (PET). A first adhesive layer is disposed on the first surface of the base layer. The first adhesive layer comprises methyl acrylic adhesive. A second adhesive layer is disposed on the second surface of the base layer. The second adhesive layer comprises methyl acrylic adhesive. A plurality of microfluidic channels extends through each of the base layer, the first adhesive layer, and the second adhesive layer.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: September 10, 2024
    Assignee: ILLUMINA, Inc.
    Inventors: Maxwell Zimmerley, LiangLiang Qiang, M. Shane Bowen, Steven H. Modiano, Dajun Yuan, Randall Smith, Arthur J. Pitera, Hai Quang Tran, Gerald Kreindl
  • Publication number: 20220250066
    Abstract: An interposer for a flow cell comprises a base layer having a first surface and a second surface opposite the first surface. The base layer comprises black polyethylene terephthalate (PET). A first adhesive layer is disposed on the first surface of the base layer. The first adhesive layer comprises methyl acrylic adhesive. A second adhesive layer is disposed on the second surface of the base layer. The second adhesive layer comprises methyl acrylic adhesive. A plurality of microfluidic channels extends through each of the base layer, the first adhesive layer, and the second adhesive layer.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 11, 2022
    Applicant: ILLUMINA, Inc.
    Inventors: Maxwell Zimmerley, LiangLiang Qiang, M. Shane Bowen, Steven H. Modiano, Dajun Yuan, Randall Smith, Arthur J. Pitera, Hai Quang Tran, Gerald Kreindl
  • Publication number: 20200009556
    Abstract: An interposer for a flow cell comprises a base layer having a first surface and a second surface opposite the first surface. The base layer comprises black polyethylene terephthalate (PET). A first adhesive layer is disposed on the first surface of the base layer. The first adhesive layer comprises methyl acrylic adhesive. A second adhesive layer is disposed on the second surface of the base layer. The second adhesive layer comprises methyl acrylic adhesive. A plurality of microfluidic channels extends through each of the base layer, the first adhesive layer, and the second adhesive layer.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 9, 2020
    Applicant: ILLUMINA, Inc.
    Inventors: Maxwell Zimmerley, LiangLiang Qiang, M. Shane Bowen, Steven H. Modiano, Dajun Yuan, Randall Smith, Arthur J. Pitera, Hai Quang Tran, Gerald Kreindl
  • Publication number: 20160380145
    Abstract: Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.
    Type: Application
    Filed: February 3, 2015
    Publication date: December 29, 2016
    Inventors: Eugene A. Fitzgerald, Arthur J. Pitera, Steven A. Ringel
  • Patent number: 9178095
    Abstract: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 3, 2015
    Assignee: 4Power, LLC
    Inventors: John J. Hennessy, Andrew C. Malonis, Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Publication number: 20140166066
    Abstract: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Inventors: John J. Hennessy, Andrew C. Malonis, Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 8604330
    Abstract: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate. In one instance, a method of forming a solar-cell array with integrated bypass diodes comprising: providing a semiconductor substrate, a first cell comprising a SiGe p-n junction or SiGe p-i-n junction, one or more second cells each comprising a III-V semiconductor p-n junction or III-V semiconductor p-i-n junction; forming a bypass diode that is discrete and laterally separate from its associated solar cell and comprises an unremoved portion of the first cell, the formation comprising removing an unremoved portion of the one or more second cells thereover.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 10, 2013
    Assignee: 4Power, LLC
    Inventors: John J. Hennessy, Andrew C. Malonis, Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 8116109
    Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: February 14, 2012
    Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
  • Publication number: 20110143495
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 16, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Publication number: 20110132445
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: May 28, 2010
    Publication date: June 9, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Publication number: 20110124146
    Abstract: In various embodiments, solar cells include a junction including SiGe, a junction including at least one III-V material, and may be formed on silicon substrates and/or with silicon-based capping layers thereover.
    Type: Application
    Filed: May 28, 2010
    Publication date: May 26, 2011
    Inventors: Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 7933133
    Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: April 26, 2011
    Assignee: Contour Semiconductor, Inc.
    Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
  • Publication number: 20100116329
    Abstract: Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.
    Type: Application
    Filed: May 29, 2009
    Publication date: May 13, 2010
    Inventors: Eugene A. Fitzgerald, Arthur J. Pitera, Steven A. Ringel
  • Publication number: 20100116942
    Abstract: Solar cells include a substrate consisting essentially of silicon, a first junction disposed over the substrate, the first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and a cap layer disposed over the first junction, the cap layer comprising silicon.
    Type: Application
    Filed: May 29, 2009
    Publication date: May 13, 2010
    Inventors: Eugene A. Fitzgerald, Arthur J. Pitera, Steven A. Ringel
  • Publication number: 20090225579
    Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
    Type: Application
    Filed: November 5, 2008
    Publication date: September 10, 2009
    Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
  • Patent number: 7202124
    Abstract: A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a particle-confining region proximate the tensilely strained layer. The method also includes introducing particles into the donor wafer to a depth below the surface, and accumulating at least some particles within the tensilely strained gettering layer. Next, the method includes initiating a cleaving action so as to separate at least one of the material layers form the substrate. The tensilely strained gettering layer may accumulate particles and/or point defects and reduce the implantation dose and thermal budget required for cleaving.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Arthur J. Pitera