Patents by Inventor Arthur J. Tysor

Arthur J. Tysor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6745345
    Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The testing method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.
    Type: Grant
    Filed: December 4, 2000
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Rafael G. Cabezas, Dhirendra Dhopeshwarkar, Robert G. Kovacs, Arthur J. Tysor
  • Patent number: 6684180
    Abstract: An apparatus, system and method for reporting field replaceable unit (FRU) replacements to a user are provided. The apparatus, system and method identify a FRU Replacement Order for an identified system error and then determines which of the FRUs in the FRU Replacement Order have already been replaced within a predetermined period of time from the current time. Those FRUs identified as having already been replaced are then flagged. The FRU Replacement Order is then output to the user with the flagged FRUs being output in a different manner than the other FRUs in the FRU Replacement Order.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: January 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Edwards, Margaret E. Gretta, Arthur J. Tysor
  • Publication number: 20020138235
    Abstract: An apparatus, system and method for reporting field replaceable unit (FRU) replacements to a user are provided. The apparatus, system and method identify a FRU Replacement Order for an identified system error and then determines which of the FRUs in the FRU Replacement Order have already been replaced within a predetermined period of time from the current time. Those FRUs identified as having already been replaced are then flagged. The FRU Replacement Order is then output to the user with the flagged FRUs being output in a different manner than the other FRUs in the FRU Replacement Order.
    Type: Application
    Filed: March 8, 2001
    Publication date: September 26, 2002
    Applicant: IBM Corporation
    Inventors: Mark S. Edwards, Margaret E. Gretta, Arthur J. Tysor
  • Publication number: 20020095624
    Abstract: A method for testing a computer bus using a bridge chip having a freeze-on-error option that enables a computer system's central processing unit (CPU) to recover and continue processing even when the computer bus is not functional. The teeting method of the present invention remains transparent to a user and can be accomplished while performing standard diagnostics tests. In general, the present invention injects an input/output (I/O) error into a specific bus slot of the computer bus to test the functionality (such as the error recovery capability) of the bus. The present invention then recovers from the failure condition without having the computer system shutdown or stop working and without having to restart the computer system. More specifically, the method for testing a computer bus according to the present invention includes enabling the freeze-on-error option on the bridge chip, injecting an error into the specified computer bus slot and recovering from the injected error.
    Type: Application
    Filed: December 4, 2000
    Publication date: July 18, 2002
    Applicant: International Business Machines Corporation
    Inventors: Rafael G. Cabezas, Dhirendra Dhopeshwarkar, Robert G. Kovacs, Arthur J. Tysor