Patents by Inventor Arthur K. Lin

Arthur K. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming an integrated circuit substrate
    Patent number: 6858475
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: February 22, 2005
    Assignee: Intel Corporation
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • METHOD OF FORMING AN INTEGRATED CIRCUIT SUBSTRATE
    Publication number: 20040266070
    Abstract: A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Charan K. Gurumurthy, Hamid Azimi, Arthur K. Lin
  • Method of dissipating static electric charge from a chip assembly during a manufacturing operation
    Patent number: 6764877
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Grounding of package substrates
    Publication number: 20030137038
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 24, 2003
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Grounding of package substrates
    Patent number: 6566741
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • GROUNDING OF PACKAGE SUBSTRATES
    Publication number: 20020105064
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Application
    Filed: October 21, 1999
    Publication date: August 8, 2002
    Inventors: ARTHUR K. LIN, ROBERT A. ANDERSON, KULJEET SINGH