Patents by Inventor Arthur Learn

Arthur Learn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070184656
    Abstract: A wafer processing cluster tool and method of operation provides one or more gas cluster ion beam processing chambers in possible combination with a deposition chamber and/or a cleaning chamber for performing sequential processing steps including, GCIB processing in a reduced pressure atmosphere.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 9, 2007
    Applicant: TEL EPION INC.
    Inventors: Steven Sherman, Arthur Learn, Robert Geffken, John Hautala
  • Publication number: 20070184655
    Abstract: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided. Various cluster tool configurations including gas-cluster ion-beam processing modules for copper capping, cleaning, etching, and film formation steps are disclosed.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 9, 2007
    Applicant: TEL Epion Inc.
    Inventors: Arthur Learn, Steven Sherman, Robert Geffken, John Hautala
  • Publication number: 20060108912
    Abstract: A protected faceplate structure of a field emission display device is disclosed in one embodiment. Specifically, in one embodiment, the present invention recites a faceplate of a field emission display device wherein the faceplate of the field emission display device is adapted to have phosphor containing wells disposed above one side thereof. The present embodiment is further comprised of a barrier layer which is disposed over the one side of said faceplate which is adapted to have phosphor containing wells disposed thereabove. The barrier layer of the present embodiment is adapted to prevent degradation of the faceplate. Specifically, the barrier layer of the present embodiment is adapted to prevent degradation of the faceplate due to electron bombardment by electrons directed towards the phosphor containing wells.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Bob Mackey, Duane Haven, Arthur Learn, John Porter, Theodore Fahlen, Shiyou Pei, William Cummings
  • Publication number: 20060105570
    Abstract: Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 18, 2006
    Applicant: Epion Corporation
    Inventors: John Hautala, Steven Sherman, Arthur Learn, Robert Geffken