Abstract: An apparatus includes an integrated circuit that includes low side power supply circuitry that provides an output voltage for H-bridge circuitry. The low side power supply circuitry includes one transistor that provides one current to the output of the low side power supply circuitry in response to the output voltage of the low side power supply circuitry dropping below a quiescent level. The low side power supply circuitry also includes a second transistor that controls the conduction state of a third transistor, based at least in part, upon the first transistor providing the first current to the output of the low side power supply circuitry. The third transistor provides a second current to the output of the low side power supply circuitry.

Abstract: An apparatus includes an integrated circuit that includes low side power supply circuitry that provides an output voltage for H-bridge circuitry. The low side power supply circuitry includes one transistor that provides one current to the output of the low side power supply circuitry in response to the output voltage of the low side power supply circuitry dropping below a quiescent level. The low side power supply circuitry also includes a second transistor that controls the conduction state of a third transistor, based at least in part, upon the first transistor providing the first current to the output of the low side power supply circuitry. The third transistor provides a second current to the output of the low side power supply circuitry.

Abstract: A shift register comprising a plurality of memory cells serially coupled together along a signal bus. Each one of the plurality of memory cells comprises a first amplifier, fed by an input logic signal, for amplifying and inverting the logic state of the input logic signal. A first storage section is included for either enabling storage in the first storage section of an electric charge corresponding to the voltage level of the amplified and inverted input logic signal, or disabling storage in the first storage section of the electric charge, selectively in response to a first control signal. The stored electric charge is converted to an intermediate logic signal having a predetermined voltage level. Each memory cell additionally includes a second amplifier, fed by the intermediate logic signal, for amplifying and inverting the logic state of the intermediate logic signal.

Abstract: A field effect transistor (FET) logic gate wherein a plurality of FETs is coupled to an output enhancement mode FET through a noise immunity circuit, such noise immunity circuit including a Schottky diode. A biasing network ensures that any conducting one of the input transistors produces a forward voltage drop between its input and output less than the forward drop of the Schottky diode circuit ensuring that the voltage at the gate electrode of the output transistor is less than the threshold voltage of such output transistor in the presence of noise. In one embodiment the logic gate includes a coupling FET having a gate electrode coupled to the gate electrode of the output transistor through the noise immunity Schottky diode circuit, and a source electrode coupled to the plurality of input transistors.

Abstract: A signal processor having a plurality of charge transfer devices adapted for coupling to an input signal source. Each one of such devices produces a sample of the input signal in response to a sampling signal. An input shift register having a plurality of serially coupled stages is provided, each one of such stages being coupled to a corresponding one of the charge transfer devices. Circuitry is included for enabling the sampling signal to be sequentially produced at an output of each one of the serially coupled stages, enabling sequential samples of the input signal to be produced in corresponding ones of the charge transfer devices.

Abstract: A charge transfer device having a source diffusion region, an isolation gate region, a reference voltage gate region and an input signal gate region disposed contiguously along such device, the isolation gate region being adapted for coupling to a pulse voltage source, the duration of such pulse being related to a predetermined sampling interval (and therefore related to the bandwidth of an input signal being sampled), the reference voltage gate region being adapted for coupling to a reference voltage source and the input signal gate region being adapted for coupling to the input signal. During each clock interval prior to the sampling interval the source diffusion region is pulsed, thereby enabling charge to pass from such region into the reference voltage gate region and the input gate region.

Abstract: A logic gate having a first depletion mode field effect transistor with a gate electrode adapted for coupling to a control signal source, a second depletion mode field effect transistor and an enhancement mode field effect transistor, such enhancement mode field effect transistor being serially connected to the second depletion mode transistor. The second depletion mode transistor and the enhancement field effect transistor are fed by the first depletion mode transistor. One of such serially connected transistors has a Schottky gate contact. With such arrangement the logic gate includes a "complementary" pair of relatively short channel length devices fed by a relatively short channel length device to provide low static power dissipation and large output capacitance drive capability.

Abstract: A transversal filter which utilizes a charge transfer delay line in combination with a plurality of source-follower pairs or their equivalent to tap the delay line and a plurality of transistors fabricated and disposed to proportionately weight, polarize, error-compensate and differentially sum the tapped signals in a single operation.