Abstract: A plurality of modules are connected in a series and addresses are automatically assigned to the modules upon the application of power. At that time, a module sends a signal to all of the other modules which causes a first timer to be started in each module. After a predefined period, an initial module, at one end of the series, sends a timing signal to the next module in the series. Each module upon receiving a timing signal starts a second timer, delays for the predefined period, and then sends a timing signal to the next module in the series. When terminal module at the opposite end of the series receives a timing signal, that module sends a second signal to all of the modules which causes the modules to stop all of the first and second timers. Each module then uses the values of its respective timers to derive a unique address.