Abstract: A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

Abstract: A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.

Abstract: A monitor for selectively detecting and recording conditions at selected points within a system during operation includes trigger logic connected from first selected points and responsive to selected conditions occurring at each of the first points for generating corresponding trigger outputs representing the occurrence of the selected conditions and a silo bank memory having a sub-silo for each second point. Each sub-silo has a first sub-silo segment with data inputs connected from the corresponding second point for recording data from the second point and a second sub-silo segment with data inputs connected from a time stamp generator.

Abstract: A monitor device for selectively detecting and recording conditions at selected points within a system during operation, including a trigger enable memory for storing selectable trigger enabling codes wherein each code corresponds to a trigger signal representing the occurrence of a corresponding condition to be detected, a trigger generation device connected from first selected points and responsive to selected conditions thereupon for generating the trigger signals representing the occurrence of selected conditions, a trigger output device responsive to the enabling codes and the trigger signals for providing trigger outputs upon the occurrence of a trigger signal corresponding to a selected trigger enabling code, and a silo bank memory connected from second selected points and responsive to the trigger outputs for recording conditions present at the second points.

Abstract: A monitoring means for selectively detecting and recording signals representing at selected points within a system, includes trigger generation logic responsive to selected bus signals for generating trigger signals representing the occurrence of selected conditions, and a recording memory for recording the conditions thereupon, a trigger selection logic for selecting trigger outputs corresponding to the trigger signals. The trigger selection logic includes a trigger enabling memory for storing selectable trigger enabling codes, wherein each enabling code corresponds to a trigger signal, and trigger output logic responsive to the trigger enabling codes and to the trigger signals for providing trigger outputs. The trigger enabling codes include bus enabling codes representing selected conditions on a bus of the system, trigger sequence enabling codes corresponding to sequential combinations of trigger signals and external trigger enabling codes corresponding to triggers external to the system.

Abstract: A monitor for selectively detecting and recording conditions at selected points within a system includes a trigger memory for storing patterns of trigger signals, wherein each pattern of trigger signals corresponds to a selected condition to be detected on first points of the system. The trigger memory includes a first port having a read address input connected from the first points and a data output connected to trigger output logic for providing patterns of trigger signals corresponding to the conditions to be detected. Each pattern of trigger signals is stored in the trigger memory location whose address corresponds to a pattern of signals from the first points representing the corresponding condition to be detected. The trigger memory is a dual port memory having a second port with a write address input and a data input for receiving trigger patterns to be stored therein.

Abstract: A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Abstract: A method and device for filleting fish using an adjustable cutting blade, having a cutting edge mounted between first and second parallel legs which are rigidly connected by a base portion, opposed to the cutting blade. The length and curvature of the blade may be adjusted to conform to the thickness and roundness of the fish to be filleted.

Abstract: A minicomputer system is disclosed having a bus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling an alternate route for issuing instructions from one processor to another. The logic detects information that is not to be transferred to the I/O devices and accordingly reroutes it back to the central processor and/or subprocessors.

Abstract: A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.

Abstract: A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Abstract: A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Abstract: In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.

Abstract: A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.

Abstract: Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.

Abstract: Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.