Abstract: A circuit board includes reference plane layers and a dielectric between the reference plane layers. A resistive element is also provided between the reference plane layers to provide a resistive path between the reference plane layers. Optimally, a decoupling capacitor is provided having a first electrode electrically connected to the resistive element, and a second electrode electrically connected to one of the reference plane layers.

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.

Abstract: A circuit board includes first and second reference plane layers. A first decoupling capacitor is mounted to a surface of the first reference plane layer, and a second decoupling capacitor is mounted to a surface of the second reference plane layer. Vias extend generally along a first direction through the circuit board. The first and second decoupling capacitors are aligned generally along the first direction to increase an amount of space through which the vias are extendable.

Abstract: A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.

Abstract: A circuit board includes multiple segments, with a first segment having plural signal layers and a second segment having plural signal layers. Signal paths provided by signal layers of the first segment exhibit higher speed signal transmission capability than signal paths provided by the signal layers of the second segment.

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to.

Abstract: A method and apparatus to provide a shield assembly for a connector, with the shield assembly having a cover to enclose the connector and a neck portion adapted to surround an outer surface of a portion of the cable. An inner surface of the neck portion makes contact with the outer surface of the cable. When the cable carries a high frequency signal, a capacitive impedance is provided between the neck portion and an outer shield of the cable to reduce electromagnetic signal leakage. Alternatively, the neck portion can make electrical contact with the cable shield, either by use of elements protruding from the inner surface of the neck portion or by removing an insulating jacket of the cable.

Abstract: A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.

Abstract: A test mechanism includes test equipment to measure frequency-domain data, such as scattering or S parameters. The S parameters are transformed to a different type of network parameters, such as transmission or T parameters. Contributions of test fixtures can be easily removed for the overall T-parameter matrix of a device under test connected in cascade with the test fixture. The test mechanism provides accurate measurement of a device under test represented by a multi-port (greater than two ports) network that is cascaded with another multi-port network representing the test fixture.

Abstract: A method and apparatus to provide a shield assembly for a connector, with the shield assembly having a cover to enclose the connector and a neck portion adapted to surround an outer surface of a portion of the cable. An inner surface of the neck portion makes contact with the outer surface of the cable. When the cable carries a high frequency signal, a capacitive impedance is provided between the neck portion and an outer shield of the cable to reduce electromagnetic signal leakage. Alternatively, the neck portion can make electrical contact with the cable shield, either by use of elements protruding from the inner surface of the neck portion or by removing an insulating jacket of the cable.

Abstract: An electric circuit board including EMI shielding. The board comprises a substrate including top and bottom surfaces and at least one internal ground layer, the internal ground layer being electrically insulated from the external surfaces of the substrate. A plurality of vias are formed in the substrate near the edges of the substrate, each via providing an opening from the surface of the substrate to the internal ground layer A metal plating is applied to the vias, the edges of the substrate and the perimeter of the surface of the substrate, the metal plating along the substrate perimeter being applied over the plated-up vias to electrically connect the ground plane with the metal plating applied to the edges of the substrate.

Abstract: A multi-chip module wherein electrical components, such as integrated circuit devices, are packaged in a three dimensional arrangement. The multi-chip module includes a first, or upper, substrate including a signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected to the signal layer. The module further includes a second, or internal, substrate, also including a first signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected with the signal layer formed on the top surface of the second substrate. The second substrate includes a cavity through the substrate corresponding to each integrated circuit device mounted thereto.

Abstract: A printed circuit board backpanel uses stripline construction to allow emitter coupled logic. (ECL) signals and transistor-transistor logic (TTL) signals on the same signal layer, while providing electromagnetic interference (EMI) emission control.