Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: Provided are computing systems, methods, and platforms that automatically produce production-ready machine learning models and deployment pipelines from minimal input information such as a raw training dataset. In particular, one example computing system can import a training dataset associated with a user. The computing system can execute an origination machine learning pipeline to perform a model architecture search that selects and trains a machine learning model for the training dataset. Execution of the origination machine learning pipeline can also result in generation of a deployment machine learning pipeline configured to enable deployment of the machine learning model (e.g., running the machine learning model to produce inferences and/or optionally other tasks such as re-training and/or re-tuning the model).

Abstract: A golf swing training apparatus is disclosed. The invention includes a harness for use in connection with a bifurcated training apparatus having two operative elements, including an upper grip portion and a lower slide portion, the portions configured to be cooperatively engaged both with a golf club and each other in a defined cooperative manner. When assembled in the preferred truncated frustoconical structure, the lower slide portion is axially slidable along a length of golf club handle to assist the golfer to learn a desired swing position.

Abstract: A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware—i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium—and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary.

Abstract: A modular telecommunication test system is presented including a portable computer system and at least one portable telecommunication test module located external to the computer system. The portable computer system stores a telecommunication test application (e.g., in a memory system). Each test module includes a communication port having an electrical connector, and is thus adapted for coupling to the portable computer system. Each test module also includes electrical circuitry for performing a set of telecommunication tests, wherein each test involves making at least one electrical measurement upon a telecommunication service installation. In coupling a given test module to the portable computer system, a user configures the test system to perform the set of telecommunication tests associated with the given test module. The at least one test module is selected from a group of test modules, each configured to perform telecommunication tests upon a different type of telecommunication service installation.

Abstract: A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware—i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium—and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary.

Abstract: An apparatus for receiving an asynchronous data signal may include a clock generator that generates a clock signal having a frequency approximately equal to the bit rate of the asynchronous data signal. An edge detector may detect transitions of the asynchronous data signal. A dead-band detector may detect when a transition of the clock signal used to sample the data signal occurs within a predetermined amount of time of a transition of the asynchronous data signal so that data sampled on that transition of the clock signal may be invalid. The phase of the clock signal may be adjusted if the transition of the clock signal occurs within this predetermined amount of time.

Abstract: A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware—i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium—and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary.

Abstract: A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register.