Abstract: A method and circuit employ digital techniques in processing an input signal of a first frequency to develop an output signal of a second frequency that is a multiple of the first frequency. During each cycle of the input signal, a presettable down counter (146) is decremented from its maximum value at a rate of 1/T.sub.1. The digital word appearing at the output of the down counter at the end of the cycle is programmed into an up counter (278) that is clocked at a rate of 1/T.sub.2. The frequency of the signal developed at the overflow output (336) of the up counter is divided by two by a flip-flop (342) whose output (348) provides a signal of a frequency which is T.sub.1 /2T.sub.2 times that of the input signal. The frequency of the output signal changes after one cycle of a change in frequency of the input signal. The frequency multiplication factor can be a noninteger value.