Abstract: An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

Abstract: An integrated circuit is provided that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

Abstract: An integrated circuit that contains a coaxial signal line formed at least partially within a silicon-containing substrate. The coaxial signal line comprises an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length. A method of preparing such an integrated circuit having said coaxial signal line formed at least partially within a silicon-containing substrate is also disclosed herein.

Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Abstract: In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.

Abstract: A portable liquid dispensing apparatus for plant care having a microprocessor timer assembly (7) which communicates to a solenoid (1) that when activated moves the spring valve (2) to open position allowing air into the container (4) receiving air pressure inside the container (4) thereby getting gravity fed liquid flow out of liquid outlet (9).

Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.

Abstract: An apparatus and method for improving planarity of chemical-mechanical polishing of substrates are provided. The apparatus includes a platen having a planar surface upon which a polishing pad is removably affixed. The pad has an exposed planar surface, and a carrier removably holds the substrate against the planar surface. The apparatus includes a slurry distribution system and a slurry removal system. The slurry distribution system provides slurry to an instantaneous interface area of the substrate and planar surface through the platen and pad, while the slurry removal system removes slurry from the instantaneous interface area through the pad and the platen, notwithstanding rotation of the platen and/or substrate, as well as linear movement of the substrate relative to the rotating platen.

Abstract: Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang structures. The film spacers may be used for a variety of applications, such as sidewall imaging, control of dopant diffusion in an FET, formation of borderless contacts, and the manufacture of a resistor from an FET.

Abstract: Disclosed is a method for separating mycotoxin-contaminated grains, kernels, seeds and nuts, from uncontaminated whole grain seeds, whole or split kernel nuts and seeds to obtain a substantially uncontaminated supply source of these foods. The separate contaminated source can be further processed to lower the mycotoxin contamination. The process involves the separation of the mycotoxin or aflatoxin-containing materials by floating the aflatoxin-contaminated foods in a liquid having a specific gravity of from about 0.9 to about 1.2. A highly preferred process uses dynamic flotation.

Abstract: An apparatus for X-ray examination is used for so-called mammagraphic work. It includes an X-ray tube, a supporting surface for the exposure material and a compressing device. The invention is particularly characterized in that a constant distance is maintained between the X-ray tube and the supporting surface for the exposure material and in that the compressing device is adjustable independently from the X-ray tube and/or the supporting surface. By way of example, the compressing device may be a compression tube supported so as to be movable in the direction toward the supporting surface.