Patents by Inventor Arthur Smith, Jr.

Arthur Smith, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160081413
    Abstract: The invention relates to a venetian mask wherein the strap that holds the mask to the face is removed and replaced with two temple arms extending to on or around the ears of the wearer or sides of the head. The temple arms or devices secure the mask to the head in a more comfortable manner. Taking off and putting on a mask is now easy due to the inventions improvement.
    Type: Application
    Filed: October 1, 2013
    Publication date: March 24, 2016
    Inventor: Roland Arthur Smith, JR.
  • Publication number: 20160079813
    Abstract: The invention relates to a propulsion device for a space craft wherein matter is accelerated to increase its mass and therefor its gravity. A method utilizing Albert Einsteins theory related to the increase in mass with acceleration. Accelerated mass exudes gravity, which can be used to pull objects through space.
    Type: Application
    Filed: October 2, 2013
    Publication date: March 17, 2016
    Inventor: Roland Arthur Smith, JR.
  • Publication number: 20160075454
    Abstract: The invention relates to aerospace fuselages or space vehicles comprising a spherical shape used to hold at least one propulsion device. A method of providing a way to correctly move, stop, and change directions in space since multi-directional propulsion is now available at any instant in time without the need to rotate a fuselage. when using a plurality of propulsion devices distributed on or within the bulkhead of the spherical fuselage.
    Type: Application
    Filed: December 5, 2013
    Publication date: March 17, 2016
    Inventor: Roland Arthur Smith, JR.
  • Patent number: 5323069
    Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a generally rectangular matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical rows of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a plurality of logic cell I/O pins located at the periphery of the matrix and connectable to the logic cells in the rows and columns at the periphery of the matrix. Furthermore, the array includes a plurality of express bus I/O pins directly connectable to the express busses.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: June 21, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Arthur Smith, Jr.
  • Patent number: 5298805
    Abstract: A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Tim Garverick, Jim Sutherland, Sanjay Popli, Venkata Alturi, Arthur Smith, Jr., Scott Pickett, David Hawley, Shao-Pin Chen, Shankar Moni, Benjamin S. Ting, Rafael C. Camarota, Shin-Mann Day, Frederick Furtek