Abstract: In general, various aspects of the techniques described in this disclosure provide time synchronization for encrypted traffic in a computer network. In one example, the disclosure describes an apparatus, such as a network device, having a control unit for a network device in a computerized network having a topology of network devices; and a forwarding unit operative to determine a release time for sending a synchronization packet in accordance with a time synchronization protocol; modify the synchronization packet to include a release timestamp specifying the release time; sending a time value via sideband data associated with the synchronization packet, wherein the time value is based on the release time specified by the release timestamp; and schedule transmission of the synchronization packet for a time corresponding to the time value in the sideband data, the synchronization packet to be transmitted to a destination network device.

Abstract: In general, various aspects of the techniques described in this disclosure provide time synchronization for encrypted traffic in a computer network. In one example, the disclosure describes an apparatus, such as a network device, having a control unit for a network device in a computerized network having a topology of network devices; and a forwarding unit operative to determine a release time for sending a synchronization packet in accordance with a time synchronization protocol; modify the synchronization packet to include a release timestamp specifying the release time; sending a time value via sideband data associated with the synchronization packet, wherein the time value is based on the release time specified by the release timestamp; and schedule transmission of the synchronization packet for a time corresponding to the time value in the sideband data, the synchronization packet to be transmitted to a destination network device.

Abstract: A synchronizing circuit receives an external signal and yields an output that is synchronized with the system clock and operates at the frequency of the external signal. The signal output from the synchronizing circuit is fed into the clock-enable input of the storage element, and the system clock signal is fed into the clock input of the storage element. Because the clock-enable signal triggers the storage element, the storage element is driven at the external signal frequency. Clock skew is eliminated because the system clock used for the clock input to the storage element is skew-controlled.

Abstract: A burn-in system for integrated circuits (ICs) generates thorough input stimuli from within the burn-in chamber. A very high node-toggle percentage within the IC being exercised is achieved, similar to that of a dynamic burn-in oven, even though the burn-in system of this invention has a cost and complexity similar to that of a static burn-in oven. This provides a cost-effective and reliable way to reduce the infant mortality of the ICs being exercised, or to estimate the longevity of the batch of ICs from which they came. The input-stimuli generator is based on a special-purpose burn-in controller IC. To better withstand the environmental stress within the burn-in chamber, the burn-in controller IC is fabricated using a robust IC technology, is operated at its nominal supply voltage and includes continuous fault tolerance features (such as self-test and/or voting). It is fully programmable to allow the same burn-in controller to be used with a variety of types of ICs being exercised.

Abstract: A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispatched instructions are valid or invalid. The pipeline executes the dispatched instructions using selected operands in the pipeline and generates operands in response. The working register file stores the generated operands before the executed instructions are determined to be valid or invalid by the dispatch controller such that the stored operands may be subsequently selected for use in executing an instruction in the pipeline. The architectural register file stores the generated operands for those of the executed instructions that are determined to be valid by the dispatch controller and transfer operands currently stored therein when one of the executed instructions is determined to be invalid by the dispatch logic.

Abstract: A method and device for moving a probe assembly into soft contact with a work surface includes initially placing the probe into an approach position. Advancement of the probe along a substantially perpendicular path toward the work surface is then controlled by applying a restraining force on the probe. This resisting force is decreased until the weight of the probe assembly just overcomes the static friction forces that are acting on the probe. After the static friction forces are overcome, the probe advances along a path toward the work surface. By monitoring this advancement, soft contact of the probe with the work surface can be determined when the velocity of the probe changes to zero. First, the position of the probe can be monitored to advance the probe along the path through a known travel distance. Second, the velocity of probe advancement can be monitored to indicate soft contact when velocity changes to zero.

Abstract: A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction type as performance critical arithmetic instructions and non-performance critical arithmetic instructions. The execution unit comprises a performance critical pipeline to execute the performance critical arithmetic instructions. The execution unit also comprises a non-performance critical pipeline to execute the non-performance critical arithmetic instructions.

Abstract: A simplified comparison of register designations by using a window delta which indicates how much the window of an instruction differs from the current window register designation. Where registers are shared, the windows will either be the same or differ by one. Thus, a single bit can be used to indicate the window delta, and in combination with the logical register address, can be used to quickly determine whether there is a register match between instructions.

Abstract: A burn-in system for integrated circuits (ICs) generates thorough input stimuli from within the burn-in chamber. A very high node-toggle percentage within the IC being exercised is achieved, similar to that of a dynamic burn-in oven, even though the burn-in system of this invention has a cost and complexity similar to that of a static burn-in oven. This provides a cost-effective and reliable way to reduce the infant mortality of the ICs being exercised, or to estimate the longevity of the batch of ICs from which they came. The input-stimuli generator is based on a special-purpose burn-in controller IC. To better withstand the environmental stress within the burn-in chamber, the burn-in controller IC is fabricated using a robust IC technology, is operated at its nominal supply voltage and includes continuous fault tolerance features (such as self-test and/or voting). It is fully programmable to allow the same burn-in controller to be used with a variety of types of ICs being exercised.

Abstract: A dependency checking method includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address.

Abstract: A dependency checking apparatus includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an indication within the scoreboard. Each double precision register which does not overlap with single precision registers maps to an indication within the scoreboard. Double precision registers which overlap single precision registers map to the set of indications corresponding to the overlapping single precision registers. Dependency checking for a source operand is performed by forming a first set of indications corresponding to the double precision registers and a second set of indications corresponding to the single precision registers, then selecting a dependency indication from these sets of indications in response to the source precision and the source register address.

Abstract: A method and apparatus for determining data dependencies and enabling bypass logic in parallel. In particular, a given stage in a given execution unit will (1) compare its destination register to the destination registers of the initial stage in each execution unit, and (2) combine the result of the comparison with the propagated results of preceding stages in the given execution unit. The other stages are not checked, as this is covered by similar checking logic in the earlier stages, with the results being passed on to the subsequent stages.

Abstract: An improved method and apparatus for ordering traps in a multiscalar design to avoid pipeline delays. Execution units which generate their traps earlier in the pipeline are used to build a number of possible enable masks, for indicating which instructions should complete, using the ordering information available from the different execution units. The enable masks cover the different possibilities of trap or no trap for the execution units which produce later traps. The traps from the execution units providing a later trap indication then select from the possible enable masks depending upon whether or not a trap is indicated by such second group of execution units. The enable mask is then used to enable or disable the destination registers used by the different execution units for that group of instructions.