Patents by Inventor Arthur Tung-Tak Leung

Arthur Tung-Tak Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8020006
    Abstract: A method and network device to process network data is described. The method may comprise receiving the network data and security operation data at a security engine. The security operation data may be associated with a security operation (e.g., encryption, decryption, hashing, or the like) to be performed on the network data. The network data and the security operation data is communicated to a systolic array including a plurality of serially interconnected processing elements each defining a processing stage. Data in each processing stage may be processed in parallel to obtain processed network data. The processed data may be stored in a memory for use by a network processing module and may identify a destination of a packet in the network. In an example embodiment, decryption or encryption may be divided up into a plurality of sub-operations wherein each sub-operation is performed by a processing stage.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: September 13, 2011
    Assignee: Cisco Technology, Inc.
    Inventor: Arthur Tung-Tak Leung, Jr.
  • Patent number: 7418536
    Abstract: A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of programmable functional units and register files arranged sequentially as stages, for processing packet contexts (which contain the packet's destination address) to perform operations, under programmatic control, to determine the destination port of the router for the packet. A single stage of the systolic array may contain a register file and one or more functional units such as adders, shifters, logical units, etc., for performing, in one example, very long instruction word (vliw) operations. The processor may also include a forwarding table memory, on-chip, for storing routing information, and a cross bar selectively connecting the stages of the systolic array with the forwarding table memory.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: August 26, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Arthur Tung-Tak Leung, Anthony Li, William Lynch, Sharad Mehrotra