Patents by Inventor Artur Kolics

Artur Kolics has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230273516
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 31, 2023
    Inventors: Jeffrey MARKS, George Andrew ANTONELLI, Richard A. GOTTSCHO, Dennis M. HAUSMANN, Adrien LAVOIE, Thomas Joseph KNISLEY, Sirish K. REDDY, Bhadri N. VARADARAJAN, Artur KOLICS
  • Publication number: 20230266662
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 24, 2023
    Inventors: Jeffrey MARKS, George Andrew ANTONELLI, Richard A. GOTTSCHO, Dennis M. HAUSMANN, Adrien LAVOIE, Thomas Joseph KNISLEY, Sirish K. REDDY, Bhadri N. VARADARAJAN, Artur KOLICS
  • Publication number: 20220075260
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: November 16, 2021
    Publication date: March 10, 2022
    Applicant: Lam Research Corporation
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Patent number: 11209729
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 28, 2021
    Assignee: Lam Research Corporation
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Patent number: 10831096
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Publication number: 20200089104
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Applicant: Lam Research Corporation
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Patent number: 10514598
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 24, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Publication number: 20190363048
    Abstract: An electrically conductive structure in an integrated circuit (IC) includes a bottom metal line and a top metal line with via providing electrical interconnection between the bottom metal line and the top metal line. The via is fully aligned with both the bottom metal line and the top metal line. An electrically conductive material fills an opening formed in a dielectric material to form the via, and the electrically conductive material is directly in contact with the bottom metal line. No diffusion barrier layer and/or liner layer is between the bottom metal line and the via.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Lie Zhao, Artur Kolics, Yezdi Dordi
  • Patent number: 10262943
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20190094685
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Patent number: 10103056
    Abstract: A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 16, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Samantha Tan, Boris Volosskiy, Taeseung Kim, Praveen Nalla, Novy Tjokro, Artur Kolics
  • Patent number: 10079207
    Abstract: A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 18, 2018
    Assignee: Lam Research Corporation
    Inventor: Artur Kolics
  • Patent number: 10049921
    Abstract: Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 14, 2018
    Assignee: Lam Research Corporation
    Inventors: Nerissa Sue Draeger, Kaihan Abidi Ashtiani, Deenesh Padhi, Derek B. Wong, Bart J. van Schravendijk, George Andrew Antonelli, Artur Kolics, Lie Zhao, Patrick A. van Cleemput
  • Publication number: 20180151503
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Patent number: 9875968
    Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 23, 2018
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
  • Publication number: 20180004083
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Application
    Filed: August 30, 2017
    Publication date: January 4, 2018
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
  • Patent number: 9837312
    Abstract: Atomic layer etching (ALE) enables effective filling of small feature structures on semiconductor and other substrates, such as contacts and vias, by bottom-up fill, for example electroless deposition (ELD) of cobalt.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 5, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Samantha Tan, Taeseung Kim, Jengyi Yu, Praveen Nalla, Novy Tjokro, Artur Kolics, Keren Jacobs Kanarik
  • Publication number: 20170330831
    Abstract: A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventor: Artur Kolics
  • Patent number: 9818617
    Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick Little, Marina Polyanskaya
  • Patent number: 9778561
    Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 3, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics