Patents by Inventor Artur Kolics
Artur Kolics has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230273516Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: April 10, 2023Publication date: August 31, 2023Inventors: Jeffrey MARKS, George Andrew ANTONELLI, Richard A. GOTTSCHO, Dennis M. HAUSMANN, Adrien LAVOIE, Thomas Joseph KNISLEY, Sirish K. REDDY, Bhadri N. VARADARAJAN, Artur KOLICS
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Publication number: 20230266662Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: April 10, 2023Publication date: August 24, 2023Inventors: Jeffrey MARKS, George Andrew ANTONELLI, Richard A. GOTTSCHO, Dennis M. HAUSMANN, Adrien LAVOIE, Thomas Joseph KNISLEY, Sirish K. REDDY, Bhadri N. VARADARAJAN, Artur KOLICS
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Publication number: 20220075260Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Applicant: Lam Research CorporationInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Patent number: 11209729Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: GrantFiled: November 21, 2019Date of Patent: December 28, 2021Assignee: Lam Research CorporationInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Patent number: 10831096Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: GrantFiled: November 30, 2018Date of Patent: November 10, 2020Assignee: LAM RESEARCH CORPORATIONInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Publication number: 20200089104Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: November 21, 2019Publication date: March 19, 2020Applicant: Lam Research CorporationInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Patent number: 10514598Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: GrantFiled: August 30, 2017Date of Patent: December 24, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Publication number: 20190363048Abstract: An electrically conductive structure in an integrated circuit (IC) includes a bottom metal line and a top metal line with via providing electrical interconnection between the bottom metal line and the top metal line. The via is fully aligned with both the bottom metal line and the top metal line. An electrically conductive material fills an opening formed in a dielectric material to form the via, and the electrically conductive material is directly in contact with the bottom metal line. No diffusion barrier layer and/or liner layer is between the bottom metal line and the via.Type: ApplicationFiled: May 22, 2018Publication date: November 28, 2019Inventors: Lie Zhao, Artur Kolics, Yezdi Dordi
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Patent number: 10262943Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: January 23, 2018Date of Patent: April 16, 2019Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Publication number: 20190094685Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: November 30, 2018Publication date: March 28, 2019Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Patent number: 10103056Abstract: A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.Type: GrantFiled: March 8, 2017Date of Patent: October 16, 2018Assignee: LAM RESEARCH CORPORATIONInventors: Samantha Tan, Boris Volosskiy, Taeseung Kim, Praveen Nalla, Novy Tjokro, Artur Kolics
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Patent number: 10079207Abstract: A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.Type: GrantFiled: July 31, 2017Date of Patent: September 18, 2018Assignee: Lam Research CorporationInventor: Artur Kolics
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Patent number: 10049921Abstract: Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.Type: GrantFiled: August 20, 2014Date of Patent: August 14, 2018Assignee: Lam Research CorporationInventors: Nerissa Sue Draeger, Kaihan Abidi Ashtiani, Deenesh Padhi, Derek B. Wong, Bart J. van Schravendijk, George Andrew Antonelli, Artur Kolics, Lie Zhao, Patrick A. van Cleemput
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Publication number: 20180151503Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: ApplicationFiled: January 23, 2018Publication date: May 31, 2018Inventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Patent number: 9875968Abstract: A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.Type: GrantFiled: February 24, 2017Date of Patent: January 23, 2018Assignee: Lam Research CorporationInventors: Artur Kolics, William T. Lee, Larry Zhao, Derek Wong, Praveen Nalla, Kaihan Ashtiani, Patrick A. Van Cleemput, Yezdi Dordi
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Publication number: 20180004083Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: ApplicationFiled: August 30, 2017Publication date: January 4, 2018Inventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics
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Patent number: 9837312Abstract: Atomic layer etching (ALE) enables effective filling of small feature structures on semiconductor and other substrates, such as contacts and vias, by bottom-up fill, for example electroless deposition (ELD) of cobalt.Type: GrantFiled: October 5, 2016Date of Patent: December 5, 2017Assignee: LAM RESEARCH CORPORATIONInventors: Samantha Tan, Taeseung Kim, Jengyi Yu, Praveen Nalla, Novy Tjokro, Artur Kolics, Keren Jacobs Kanarik
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Publication number: 20170330831Abstract: A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.Type: ApplicationFiled: July 31, 2017Publication date: November 16, 2017Inventor: Artur Kolics
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Patent number: 9818617Abstract: A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.Type: GrantFiled: December 8, 2016Date of Patent: November 14, 2017Assignee: Lam Research CorporationInventors: Artur Kolics, Praveen Nalla, Xiaomin Bin, Nanhai Li, Yaxin Wang, Patrick Little, Marina Polyanskaya
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Patent number: 9778561Abstract: Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.Type: GrantFiled: January 30, 2015Date of Patent: October 3, 2017Assignee: LAM RESEARCH CORPORATIONInventors: Jeffrey Marks, George Andrew Antonelli, Richard A. Gottscho, Dennis M. Hausmann, Adrien LaVoie, Thomas Joseph Knisley, Sirish K. Reddy, Bhadri N. Varadarajan, Artur Kolics