Patents by Inventor Artur Melo Mota Costa

Artur Melo Mota Costa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for command interpretation in an electronic design automation environment
    Patent number: 11379753
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 5, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tulio Paschoalin Leao, Gabriel Guedes de Azevedo Barbosa, Artur Melo Mota Costa, Alberto Manuel Arias Drake, Guilherme Seminotti Braga, Rodrigo Fonseca Rocha Soares, Rogério de Souza Moraes, Paula Selegato Mathias, Tales Bontempo Cunha
  • Systems and methods for automatic formal metastability fault analysis in an electronic design
    Patent number: 10769008
    Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alberto Manuel Arias Drake, Andrea Iabrudi Tavares, Artur Melo Mota Costa, Fabiano Cruz Peixoto, Laiz Lipiainen Santos, Lucas Ferreira de Melo Diniz, Nathália Peixoto Reis, Patricia Sette Câmara Haizer, Regina Mara Amaral Fonseca, Tamires Vargas Capanema Franco Santos
  • Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques
    Patent number: 10204201
    Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 12, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lawrence Loh, Artur Melo Mota Costa, Breno Rodrigues Guimaraes, Fabiano Peixoto, Andrea Iabrudi Tavares