Patents by Inventor Artur Pogiel

Artur Pogiel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8356222
    Abstract: Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: January 15, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
  • Patent number: 7962820
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: June 14, 2011
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20110055646
    Abstract: Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 3, 2011
    Inventors: Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
  • Patent number: 7890827
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: February 15, 2011
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
  • Publication number: 20100257417
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Application
    Filed: June 18, 2010
    Publication date: October 7, 2010
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
  • Publication number: 20100229055
    Abstract: Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
    Type: Application
    Filed: March 5, 2010
    Publication date: September 9, 2010
    Inventors: NILANJAN MUKHERJEE, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
  • Patent number: 7743302
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: June 22, 2010
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
  • Publication number: 20090249147
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
    Type: Application
    Filed: March 17, 2009
    Publication date: October 1, 2009
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Patent number: 7509550
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: March 24, 2009
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Patent number: 7437640
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: October 14, 2008
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20080133987
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Application
    Filed: January 30, 2008
    Publication date: June 5, 2008
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
  • Patent number: 7370254
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: May 6, 2008
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
  • Patent number: 7302624
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: November 27, 2007
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20060041813
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided.
    Type: Application
    Filed: August 25, 2005
    Publication date: February 23, 2006
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20060041812
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
    Type: Application
    Filed: August 25, 2005
    Publication date: February 23, 2006
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20060041814
    Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.
    Type: Application
    Filed: August 25, 2005
    Publication date: February 23, 2006
    Inventors: Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer, Chen Wang
  • Publication number: 20040230884
    Abstract: The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
    Type: Application
    Filed: February 13, 2004
    Publication date: November 18, 2004
    Inventors: Janusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel