Abstract: An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D1) connected in parallel with the capacitive element (C), a first switching element (S1) provided in series between the first node (A) and a voltage source point, a second switching element (S2) provided between the first node (A) and a second node (Node B), a second element (D2) connected between the second switching element (S2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S1) is closed and the second switching element (S2) to charge a nodal voltage vD(t) at the first node (A). In discharge stage, the first switching element (S1) is open and the second switching element (S2) is open to enable discharging of the capacitive element (C) through the first element (D1).

Abstract: An amplifier circuit includes a resistor divider (RREF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d1, d2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (IREF) connected or connectable to the first main node (a). The resistor divider (RREF) comprises two arrays of addressable switch elements controllable by a feedback signal (sFB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T1, T2), wherein source terminals of each of the transistors (T1, T2) are connected to the second node (b), gate terminals of the transistors (T1, T2) are connected to input signals (v1, v2), drain terminals of the transistors (T1, T2) are connected to current sources (I1, I2), and bulk terminals of the transistors (T1, T2) are connected to the readout nodes (d1, d2).

Abstract: An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D1) connected in parallel with the capacitive element (C), a first switching element (S1) provided in series between the first node (A) and a voltage source point, a second switching element (S2) provided between the first node (A) and a second node (Node B), a second element (D2) connected between the second switching element (S2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S1) is closed and the second switching element (S2) to charge a nodal voltage vD(t) at the first node (A). In discharge stage, the first switching element (S1) is open and the second switching element (S2) is open to enable discharging of the capacitive element (C) through the first element (D1).

Abstract: The method for operating a UWB device having at least one transmitting antenna and/or at least one receiving antenna comprises the following steps: controlling the transmitting antenna (12) or the receiving antenna (12?) with a control pulse signal (13,13?) having a sequence of substantially sinusoidal pulses of alternating polarity and differing amplitudes and particularly having the waveform of a fifth-order Gaussian pulse signal, wherein the transmitting antenna (12) can be alternately supplied with current pulses of differing polarity and differing magnitude by switching on and off first electronic switch units (16) that are coupled to the transmitting antenna (12) and have resistances associated with the amplitudes of the pulses to be generated, wherein each first switch unit (16) has a specifiable, particularly equal, number of first switching transistors (18,19), each having substantially identical on-state resistance values (R), wherein the resistance of a first switch unit is adjusted either by using

Abstract: The method for operating a UWB device having at least one transmitting antenna and/or at least one receiving antenna comprises the following steps: controlling the transmitting antenna (12) or the receiving antenna (12?) with a control pulse signal (13,13?) having a sequence of substantially sinusoidal pulses of alternating polarity and differing amplitudes and particularly having the waveform of a fifth-order Gaussian pulse signal, wherein the transmitting antenna (12) can be alternately supplied with current pulses of differing polarity and differing magnitude by switching on and off first electronic switch units (16) that are coupled to the transmitting antenna (12) and have resistances associated with the amplitudes of the pulses to be generated, wherein each first switch unit (16) has a specifiable, particularly equal, number of first switching transistors (18,19), each having substantially identical on-state resistance values (R), wherein the resistance of a first switch unit is adjusted either by using

Abstract: The sensing device for sensing a physical parameter such as radiation, temperature or the like, comprises an analogue sensor element sensitive for the physical parameter to be sensed and outputting an analogue signal and an analogue two-digital converter (ADC) having an MOS input stage for receiving the analogue output signal of the sensor element so as to convert the analogue output signal to a digital output signal.