Abstract: A method for protecting an integrated circuit against reverse engineering including predefining a secret bit, forming a first clocked memory element having a first data input, a first data output and a first clock input in the integrated circuit, forming a second clocked memory element having a second data input, a second data output and a second clock input in the integrated circuit, forming a logic path in the integrated circuit and coupling the first data output to the second data input via the logic path and forming a clock signal line in the integrated circuit and coupling the first clock input to the second clock input via the clock signal line.

Abstract: A bit generation circuit having a plurality of signal chains, where for each chain, a first input of an input multiplexer is connected to another of the signal chains and the multiplexer is configured so that, if a control signal indicating a normal operating mode is fed to the multiplexer, the multiplexer connects the first input to the path input of the signal chain. The second input of each multiplexer is connected to the output of a bit generation trigger circuit and, for each signal chain, the multiplexer is configured so that, if a control signal indicating a secret generation mode is fed to the multiplexer, it connects the second input to the path input of the signal chain. The bit generation circuit furthermore comprises an arbiter circuit connected to the path outputs of at least two signal chains and configured to output a secret bit depending on their states.

Abstract: A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.

Abstract: The present invention relates to a base plate for a rail fastening point, in which a rail for a rail vehicle is fastened on a substrate. The base plate includes a main body with a rib structure, which from the underside assigned to the substrate is formed into the main body of the base plate and is formed by ribs and by recesses which surround the ribs and are open to the underside, and to a rail fastening point. The base plate for a rail fastening point can be manufactured in a simple, cost-effective manner and makes it possible to avoid by simple means pressing into a soft substrate. This is achieved in that the base plate additionally includes a cover fastened to the base plate after the manufacture of the main body, which covers the rib structure on the underside of the main body at least in sections.

Abstract: The present invention relates to a base plate for a rail fastening point, in which a rail for a rail vehicle is fastened on a substrate. The base plate includes a main body with a rib structure, which from the underside assigned to the substrate is formed into the main body of the base plate and is formed by ribs and by recesses which surround the ribs and are open to the underside, and to a rail fastening point. The base plate for a rail fastening point can be manufactured in a simple, cost-effective manner and makes it possible to avoid by simple means pressing into a soft substrate. This is achieved in that the base plate additionally includes a cover fastened to the base plate after the manufacture of the main body, which covers the rib structure on the underside of the main body at least in sections.

Abstract: According to various embodiments, a memory arrangement is described having a first bit line, a first precharge device for precharging the first bit line to a precharged state, a second bit line, a second precharge device for precharging the second bit line to a precharged state, a memory control apparatus that is set up to interrupt the precharging of the first bit line by the first precharge device for memory access and to interrupt the precharging of the second bit line by the second precharge device for the memory access, a memory access apparatus that is set up to follow the interruption of the precharging of the first bit line and the interruption of the precharging of the second bit line by performing the memory access and reading the state of the second bit line, and a detector that is set up to take the state of the second bit line as a basis for detecting an attack on the memory arrangement.

Abstract: In accordance with one embodiment, a circuit arrangement is provided including a circuit having a first terminal for a first supply potential and a second terminal for a second supply potential, wherein the first terminal is coupled to the first supply potential; a switch, by means of which the second terminal can be coupled to the second supply potential; a voltage source coupled to the second terminal; and a control device designed to open the switch in reaction to receiving a turn-off signal in an operating mode in which the switch is closed, and subsequently to control the voltage source in such a way that it varies the potential of the second terminal in the direction of the first supply potential.

Abstract: According to various embodiments, a memory arrangement is described having a first bit line, a first precharge device for precharging the first bit line to a precharged state, a second bit line, a second precharge device for precharging the second bit line to a precharged state, a memory control apparatus that is set up to interrupt the precharging of the first bit line by the first precharge device for memory access and to interrupt the precharging of the second bit line by the second precharge device for the memory access, a memory access apparatus that is set up to follow the interruption of the precharging of the first bit line and the interruption of the precharging of the second bit line by performing the memory access and reading the state of the second bit line, and a detector that is set up to take the state of the second bit line as a basis for detecting an attack on the memory arrangement.

Abstract: In accordance with one embodiment, a circuit arrangement is provided including a circuit having a first terminal for a first supply potential and a second terminal for a second supply potential, wherein the first terminal is coupled to the first supply potential; a switch, by means of which the second terminal can be coupled to the second supply potential; a voltage source coupled to the second terminal; and a control device designed to open the switch in reaction to receiving a turn-off signal in an operating mode in which the switch is closed, and subsequently to control the voltage source in such a way that it varies the potential of the second terminal in the direction of the first supply potential.

Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.

Abstract: A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

Abstract: An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

Abstract: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.