Patents by Inventor Arul Subbarayan

Arul Subbarayan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170010325
    Abstract: A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 12, 2017
    Inventors: Arul Subbarayan, Sachin Badole, Archana Matta, Madhura Hegde, Sergio Mier, Shankarnarayan Bhat, Michael Laisne, Glenn Mark Plowman, Prakash Krishnan