Abstract: A method and cleaning solution that removes contaminants from a dielectric material and polished surfaces of copper interconnect structures prior to an electroless deposition of a capping layer without substantially adversely affecting the interconnect formed therefrom are disclosed. The cleaning solution includes combinations of a core mixture and sulfuric acid or sulfonic compounds such as sulfonic acids that include methanesulfonic acid. In one embodiment, the core mixture includes a citric acid solution and a pH adjuster such as tetra-methyl ammonium hydroxide or ammonia. One embodiment of the method includes providing a planarized substrate, applying the cleaning solution to the substrate to simultaneously clean at least one metal feature and a dielectric material of the substrate, and depositing the metal capping layer selectively on the at least one metal feature using electroless deposition.

Abstract: Embodiments of the present invention relate to an apparatus and method of annealing substrates in a thermal anneal chamber and/or a plasma anneal chamber before electroless deposition thereover. In one embodiment, annealing in a thermal anneal chamber includes heating the substrate in a vacuum environment while providing a gas, such as noble gases, hydrogen gas, other reducing gases, nitrogen gas, other non-reactive gases, and combinations thereof. In another embodiment, annealing in a plasma chamber comprises plasma annealing the substrate in a plasma, such as a plasma from an argon gas, helium gas, hydrogen gas, and combinations thereof.

Abstract: A method of film deposition in a sub-atmospheric chemical vapor deposition (CVD) process includes (a) providing a model for sub-atmospheric CVD deposition of a film that identifies one or more film properties of the film and at least one deposition model variable that correlates with the one or more film properties; (b) depositing a film onto a wafer using a first deposition recipe comprising at least one deposition recipe parameter that corresponds to the at least one deposition variable; (c) measuring a film property of at least one of said one or more film properties for the deposited film of step (b); (d) calculating an updated deposition model based upon the measured film property of step (c) and the model of step (a); and (e) calculating an updated deposition recipe based upon the updated model of step (d) to maintain a target film property. The method can be used to provide feedback to a plurality of deposition chambers or to control a film property other than film thickness.

Abstract: Methods and apparatus for feedback controlled polishing. A computer program product for generating feedback for chemical mechanical polishing. The product includes instructions operable to cause a processor to receive monitoring information during a current polishing cycle in which a first polishing process is performed on a substrate that includes a metal layer. The first polishing process clears the metal layer from the substrate during the current polishing cycle. The product includes instructions to calculate a representation of a clearing profile of the first polishing process. The calculation is based on the monitoring information received during the current polishing cycle. The product includes instructions to detect non-uniformity in the representation. The product includes instructions to generate, from the non-uniformity detected, feedback information for improving the uniformity of a clearing profile of the first polishing process for a subsequent polishing cycle.

Abstract: Techniques for controlling an output property during wafer processing include forwarding feedforward and feedback information between functional units in a wafer manufacturing facility. At least some embodiments of the invention envision implementing such techniques in a copper wiring module to optimize a sheet resistance or an interconnect line resistance. Initially, a first wafer property is measured during or after processing by a plating process. Subsequently, the wafer is forwarded to a polishing process. A second wafer property is then measured during or after processing by the second process. At least one of these first and second wafer properties are used to optimize the second process. Specifically, one or more target parameters of a second process recipe are adjusted in a manner that obtains a desired final output property on the wafer by using these first and second wafer properties.

Abstract: Embodiments of the invention generally provide an electrochemical plating system. The plating system includes a substrate loading station positioned in communication with a mainframe processing platform, at least one substrate plating cell positioned on the mainframe, at least one substrate bevel cleaning cell positioned on the mainframe, and a stacked substrate annealing station positioned in communication with at least one of the mainframe and the loading station, each chamber in the stacked substrate annealing station having a heating plate, a cooling plate, and a substrate transfer robot therein.

Abstract: Embodiments of the invention provide methods for depositing a material onto a surface of a substrate by using one or more electroless, electrochemical plating, CVD and/or ALD processes. Embodiments of the invention provide a method for depositing a seed layer on a substrate with an electroless process and to subsequently fill interconnect features on the substrate with an ECP process on a single substrate processing platform. Other aspects provide a method for depositing a seed layer on a substrate, fill interconnect features on a substrate, or sequentially deposit both a seed layer and fill interconnect features on the substrate. One embodiment provides a method for forming a capping layer over substrate interconnects. Methods include the use of a vapor dryer for pre- and post-deposition cleaning of substrates as well as a brush box chamber for post-deposition cleaning.

Abstract: A method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d) calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations.

Abstract: Embodiments of the invention provide a method for depositing a copper material on a substrate by an electroless deposition process and also provide a composition of an electroless deposition solution. In one embodiment, the copper material is deposited from an electroless copper solution that contains an additive, such as an inhibitor, to promote a bottom-up fill process. In one aspect, the field of the substrate may be maintained free of copper material or substantially free of copper material during the electroless deposition process. Prior to the electroless deposition process for forming the copper material, a barrier layer may be deposited on the substrate, and thereafter, a ruthenium layer may be deposited thereon. In one example, the copper material is formed during a bottom-up, electroless deposition process directly on the ruthenium layer. Alternatively, a seed layer may be formed on the ruthenium layer prior to depositing the copper material.

Abstract: The present invention generally provides an apparatus and method of processing substrates to uniformly remove any residual contamination from the surface of a substrate by use of an appropriate cleaning chemistry and contact with a cleaning medium. In one embodiment, the cleaning medium, such as is a brush or a scrubbing component that is positioned in a cleaning module. In one embodiment, the process of cleaning the surface of a substrate W is completed by “scrubbing” the surface of the substrate while using a cleaning solution that is selected to chemically etch a material from the surface of the substrate. In one aspect, the amount of material removed from the surface of a substrate is only about 10-30 Angstroms (?). In one embodiment, the substrate surface is cleaned by use of a scrubbing process that uses a fluid that doesn't react with the exposed materials on the surface of the substrate.

Abstract: A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material.

Abstract: A method for fabricating a capping layer with enhanced barrier resistance to both copper and oxygen diffusion, comprises forming a capping layer on a conductive surface of an interconnect, wherein the capping layer comprises cobalt (Co), tungsten (W), rhenium (Re), and at least one of phosphorus (P) and boron (B). In an embodiment of the invention, forming the capping layer comprises exposing the conductive surface to an electroless capping solution comprising a cobalt source, a tungsten source, a rhenium source, and at least one of a phosphorus source and a boron source, and annealing the capping layer.

Abstract: Embodiments of the invention generally provide a cluster tool that is configured to electrolessly fill features formed on a substrate. More particularly, embodiments of the invention are used to integrate the filling of an interconnect or contact level feature using an electroless fill process and material removal steps. A typical sequence for forming an interconnect includes depositing one or more non-conductive layers, etching at least one of the layer(s) to form one or more features therein, depositing a barrier layer in the feature(s) and depositing one or more conductive layers, such as copper, to fill the feature.

Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.

Abstract: Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.

Abstract: Embodiments of the invention provide a simplified method of filling contact level features formed in a semiconductor device. In general the method includes a novel method of forming a contact level feature that contains a silicide interface and a tungsten CVD deposited layer. The processes discussed below are less complex and less time consuming than other conventional contact level interconnect formation processes and thus will have an improved device yield.

Abstract: In one embodiment, a method for depositing a material on a substrate is provided which includes positioning a substrate containing a contact within a process chamber, exposing the substrate to at least one pretreatment step and depositing a fill the contact vias by an electroless deposition process. The pretreatment step contains multiple processes for exposing the substrate to a wet-clean solution, a hydrogen fluoride solution, a tungstate solution, a palladium activation solution, an acidic rinse solution, a complexing agent solution or combinations thereof. Generally, the HARC via contains a tungsten oxide surface and the shallow contact via may contain a tungsten silicide surface. In some example, the substrate is pretreated such that both vias are filled at substantially the same time by a nickel-containing material through an electroless deposition process.

Abstract: Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process.

Abstract: Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.

Abstract: Embodiments as described herein provide methods for depositing a material on a substrate during electroless deposition processes, as well as compositions of the electroless deposition solutions. In one embodiment, the substrate contains a contact aperture having an exposed silicon contact surface. In another embodiment, the substrate contains a contact aperture having an exposed silicide contact surface. The apertures are filled with a metal contact material by exposing the substrate to an electroless deposition process. The metal contact material may contain a cobalt material, a nickel material, or alloys thereof. Prior to filling the apertures, the substrate may be exposed to a variety of pretreatment processes, such as preclean processes and activations processes. A preclean process may remove organic residues, native oxides, and other contaminants during a wet clean process or a plasma etch process. Embodiments of the process also provide the deposition of additional layers, such as a capping layer.