Patents by Inventor Arulselvam Simon Jeyapalan

Arulselvam Simon Jeyapalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220395986
    Abstract: Disclosed are techniques and systems for automatically determining and correcting the levelness of a wafer handling robot end effector. The systems may use a tilt sensor or a gravitational field sensor which may be calibrated to the wafer handling robot. The output from the tilt sensor may be used to determine or estimate the tilt of an end effector of the wafer handling robot and to perform correctional positioning to reduce or eliminate the tilt, to automatically teach certain positions that have reduced tilt, to perform health checks on the robot, provide feedback to a user, etc.
    Type: Application
    Filed: October 23, 2020
    Publication date: December 15, 2022
    Inventors: Richard M. Blank, Marco Piccigallo, Eric Chan, Arulselvam Simon Jeyapalan
  • Publication number: 20220254666
    Abstract: Systems and techniques for determining and using multiple types of offsets for providing wafers to a wafer support of a wafer station of a semiconductor processing tool are disclosed; such techniques and systems may use an autocalibration wafer that may include a plurality of sensors, including a plurality of edge-located imaging sensors that may be used to image fiducials associated with two different structures located in a selected wafer station.
    Type: Application
    Filed: July 21, 2020
    Publication date: August 11, 2022
    Inventors: Hossein Sadeghi, Richard M. Blank, Peter S. Thaulad, Mark E. Emerson, Arulselvam Simon Jeyapalan, Marco Piccigallo
  • Patent number: 10509052
    Abstract: A test wafer having two spaced-apart accelerometers mounted thereon is disclosed. The accelerometers may be positioned at locations located along a common axis passing through the center of gravity of the test wafer. The test wafer may include a controller that may be used to transmit acceleration data collected by the accelerometers to another device. In some implementations, a semiconductor processing tool is provided that includes a test wafer receptacle for storing a test wafer that remains with the semiconductor processing tool and that may be retrieved by a wafer handling robot for performing a test cycle during periods when the wafer handling robot is not performing substrate transport operations.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Peter S. Thaulad, Arulselvam Simon Jeyapalan, Richard M. Blank, Tyson Lee Ringold, Victor Eduardo Espinosa, III
  • Publication number: 20180224500
    Abstract: A test wafer having two spaced-apart accelerometers mounted thereon is disclosed. The accelerometers may be positioned at locations located along a common axis passing through the center of gravity of the test wafer. The test wafer may include a controller that may be used to transmit acceleration data collected by the accelerometers to another device. In some implementations, a semiconductor processing tool is provided that includes a test wafer receptacle for storing a test wafer that remains with the semiconductor processing tool and that may be retrieved by a wafer handling robot for performing a test cycle during periods when the wafer handling robot is not performing substrate transport operations.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Peter S. Thaulad, Arulselvam Simon Jeyapalan, Richard M. Blank, Tyson Lee Ringold, Victor Eduardo Espinosa, III