Patents by Inventor Arun A. NAIR

Arun A. NAIR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230370354
    Abstract: The present disclosure provides novel solution for Network Optimization in telecommunications network that has traditionally always been driven by measuring and improving Key Performance Indicators (KPIs) of network elements vis-à-vis advancement for identification of the customers with poor experience and identification of spatial clusters of these customers to pinpoint the exact location of the problem, allowing for more targeted network optimization. The systems and methods contained in this invention enable the identification of these customers with poor experience and identifies spatial clusters of these customers to pinpoint the exact location of the problem, allowing for more targeted network optimization. This disclosure provides solution by aggregating a multitude of metrics pertinent to the user’s voice, data and coverage experience and deriving a single KPI, it is possible to benchmark and correspondingly track and improve their experience.
    Type: Application
    Filed: March 28, 2022
    Publication date: November 16, 2023
    Inventors: Ajay Kumar GUPTA, Arun NAIR, Aditya GANESH, Aayush BHATNAGAR, Avinash BHARDWAJ
  • Publication number: 20230201966
    Abstract: Systems and methods are provided for generating microscale structures and/or nanoscale structures, surface profiles, and surface chemistries on medical devices. Embodiments disclosed herein utilize exposure of pulsed laser radiation on to a surface of a material by a pulsed laser. The pulsed laser according to embodiments disclosed herein is configured to emit at least one laser pulse toward the surface and thereby modify the profile of the surface in order to selectively promote or inhibit bioactivity and medical functionality of the material. By selectively promoting or inhibiting bioactivity of the material, enhanced biointegration at a cellular level may be achieved. For example, modifying the surface profile and/or surface chemistry of a first substrate material can improve adhesive and/or chemical bonding of the first material to a bioactive second coating material.
    Type: Application
    Filed: December 28, 2022
    Publication date: June 29, 2023
    Inventors: Jason Kalishek, Arun Nair
  • Patent number: 11599359
    Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 7, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun A. Nair, Ashok T. Venkatachar, Emil Talpes, Srikanth Arekapudi, Rajesh Kumar Arunachalam
  • Patent number: 11544065
    Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: January 3, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arun A. Nair, Todd Baumgartner, Michael Estlick, Erik Swanson
  • Patent number: 11526367
    Abstract: Systems and methods for translation of a digital document to an equivalent interactive User Interface (UI), receive the digital document containing content; detect a selection and placement of a plurality of form fields, based at least in part on the content; construct a UI template and corresponding object graph, based at least in part on the selection and placement of each of the plurality of form fields; wherein the UI template represents the content of the digital document according to a predefined document schema; and wherein the object graph is defined by one or more dependencies and one or more validations associated with the selection and placement of each of the plurality of form fields; parse the UI template; and render the UI template as an interactive UI for distribution to an end user based at least in part on a predefined rendering library.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 13, 2022
    Assignee: Morgan Stanley Services Group Inc.
    Inventors: Arun Nair, Anand Verma, Tushar Agarwal
  • Publication number: 20220374249
    Abstract: Systems and methods for translation of a digital document to an equivalent interactive User Interface (UI), receive the digital document containing content; detect a selection and placement of a plurality of form fields, based at least in part on the content; construct a UI template and corresponding object graph, based at least in part on the selection and placement of each of the plurality of form fields; wherein the UI template represents the content of the digital document according to a predefined document schema; and wherein the object graph is defined by one or more dependencies and one or more validations associated with the selection and placement of each of the plurality of form fields; parse the UI template; and render the UI template as an interactive UI for distribution to an end user based at least in part on a predefined rendering library.
    Type: Application
    Filed: May 21, 2021
    Publication date: November 24, 2022
    Applicant: Morgan Stanley Services Group Inc.
    Inventors: Arun NAIR, Anand Verma, Tushar Agarwal
  • Publication number: 20220174504
    Abstract: The present disclosure provides the planning of the next generation network which complements an existing telecom deployment to achieve the desired KPIs from the combined network for both macro and small cell planning in an existing network in a cost-effective method to deploy ODSC cells and Macro Cells in a heterogeneous network. Planning a next-generation network for an existing telecom operator is a large undertaking, utilizing precious man-hours and most importantly, weeks of work. Using an automated planning methodology to plan macro and small cells for a region like a city, state or even country, planners can deploy solutions to make the most optimum use of existing infrastructure. The invention proposes an automated approach to plan the preferred overlay telecom solutions in an area A being part of an existing telecom deployment.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 2, 2022
    Applicant: JIO PLATFORMS LIMITED
    Inventors: Ajay Kumar GUPTA, Arun NAIR, Aditya GANESH, Aayush BHATNAGAR,, Dharmesh CHITALIYA, Atul VERMA, Shubham GUPTA
  • Patent number: 11281466
    Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 22, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Arun A. Nair, Michael Estlick, Erik Swanson, Sneha V. Desai, Donglin Ji
  • Publication number: 20210357222
    Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Arun A. NAIR, Ashok T. VENKATACHAR, Emil TALPES, Srikanth AREKAPUDI, Rajesh Kumar ARUNACHALAM
  • Patent number: 11165726
    Abstract: In some embodiments, there is provided a system. The system may include at least one data processor and at least one memory storing instructions which, when executed by the at least one data processor, cause the apparatus to at least: in response to receiving a request to capture a screenshot at a first user equipment, identify, by a screen share service, one or more entities in a user interface being captured with the screenshot; store, by the screen share service in a persistent store, the identified one or more entities associated with the screenshot; in response to invoking the screenshot at a messaging application at a second user equipment, obtain, from the persistent store, the identified one or more entities to enable the second user equipment to present the identified one or more entities; and provide the identified one or more entities to the second user equipment.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 2, 2021
    Assignee: SAP SE
    Inventor: Arun Nair
  • Publication number: 20210157598
    Abstract: Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Neil N. Marketkar, Arun A. Nair
  • Publication number: 20210126880
    Abstract: In some embodiments, there is provided a system. The system may include at least one data processor and at least one memory storing instructions which, when executed by the at least one data processor, cause the apparatus to at least: in response to receiving a request to capture a screenshot at a first user equipment, identify, by a screen share service, one or more entities in a user interface being captured with the screenshot; store, by the screen share service in a persistent store, the identified one or more entities associated with the screenshot; in response to invoking the screenshot at a messaging application at a second user equipment, obtain, from the persistent store, the identified one or more entities to enable the second user equipment to present the identified one or more entities; and provide the identified one or more entities to the second user equipment.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventor: Arun Nair
  • Publication number: 20210117196
    Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventors: Arun A. NAIR, Michael ESTLICK, Erik SWANSON, Sneha V. DESAI, Donglin JI
  • Publication number: 20210096862
    Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Arun A. NAIR, Todd BAUMGARTNER, Michael ESTLICK, Erik SWANSON
  • Publication number: 20200242784
    Abstract: Various embodiments are disclosed for detecting, tracking and counting objects of interest in video. In an embodiment, a method of detecting and tracking objects of interest comprises: obtaining, by a computing device, multiple frames of images from an image capturing device; detecting, by the computing device, objects of interest in each frame; accumulating, by the computing device, multiple frames of object detections; creating, by the computing device, object tracks based on a batch of object detections over multiple frames; and associating, by the computing device, the object tracks over consecutive batches.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Applicant: RetailNext, Inc.
    Inventors: Imran Saleemi, Mark Jamtgaard, Arun Nair
  • Patent number: 10621735
    Abstract: Various embodiments are disclosed for detecting, tracking and counting objects of interest in video. In an embodiment, a method of detecting and tracking objects of interest comprises: obtaining, by a computing device, multiple frames of images from an image capturing device; detecting, by the computing device, objects of interest in each frame; accumulating, by the computing device, multiple frames of object detections; creating, by the computing device, object tracks based on a batch of object detections over multiple frames; and associating, by the computing device, the object tracks over consecutive batches.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 14, 2020
    Assignee: RetailNext, Inc.
    Inventors: Imran Saleemi, Mark Jamtgaard, Arun Nair
  • Publication number: 20190325588
    Abstract: Various embodiments are disclosed for detecting, tracking and counting objects of interest in video. In an embodiment, a method of detecting and tracking objects of interest comprises: obtaining, by a computing device, multiple frames of images from an image capturing device; detecting, by the computing device, objects of interest in each frame; accumulating, by the computing device, multiple frames of object detections; creating, by the computing device, object tracks based on a batch of object detections over multiple frames; and associating, by the computing device, the object tracks over consecutive batches.
    Type: Application
    Filed: November 15, 2018
    Publication date: October 24, 2019
    Inventors: Imran Saleemi, Mark Jamtgaard, Arun Nair
  • Patent number: 10134146
    Abstract: Various embodiments are disclosed for detecting, tracking and counting objects of interest in video. In an embodiment, a method of detecting and tracking objects of interest comprises: obtaining, by a computing device, multiple frames of images from an image capturing device; detecting, by the computing device, objects of interest in each frame; accumulating, by the computing device, multiple frames of object detections; creating, by the computing device, object tracks based on a batch of object detections over multiple frames; and associating, by the computing device, the object tracks over consecutive batches.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 20, 2018
    Assignee: RetailNext, Inc.
    Inventors: Imran Saleemi, Mark Jamtgaard, Arun Nair
  • Publication number: 20180158063
    Abstract: A system, method and non-transitory, computer-readable storage medium are disclosed for point-of-sale (POS) fraud detection using, POS transaction data, video data and statistical evaluations of employee behavior. In an embodiment, the POS transaction data, video data and statistical evaluations are used to examine patterns of individual employees of an organization versus metrics across all employees of the organization to identify employees that are most likely to perform a fraudulent transaction.
    Type: Application
    Filed: December 23, 2016
    Publication date: June 7, 2018
    Inventors: Mark Jamtgaard, Arun Nair
  • Publication number: 20170206669
    Abstract: Various embodiments are disclosed for detecting, tracking and counting objects of interest in video. In an embodiment, a method of detecting and tracking objects of interest comprises: obtaining, by a computing device, multiple frames of images from an image capturing device; detecting, by the computing device, objects of interest in each frame; accumulating, by the computing device, multiple frames of object detections; creating, by the computing device, object tracks based on a batch of object detections over multiple frames; and associating, by the computing device, the object tracks over consecutive batches.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 20, 2017
    Inventors: Imran Saleemi, Mark Jamtgaard, Arun Nair