Abstract: This invention describes a column redundancy arrangement in a DRAM that minimizes the timing difference between a normal and a redundant column path. A semiconductor memory device comprises memory elements arranged in rows and columns. The memory elements are accessed by energizing one or more rows and columns. A first and a second group of normal column drivers are provided for energizing associated normal memory columns in response to respective ones of column select signals. Further, a first and second redundant column driver are provided for energizing associated redundant memory columns upon receipt of a column select signal along a redundancy select line. A plurality of programmable switches are associated with the normal column drivers, for selectively steering respective ones of the column select signals to associated column drivers or the first or second of the redundant column drivers.