Abstract: Parameters of a pool of computing resources to be utilized for machine learning tasks from a set of entities are stored, including a category of the computing resources, and a post-task-completion retention period during which, after completion of a task, at least a portion of data stored at the resource is not to be deleted. A compute instance of the pool is assigned to a task requested from the set of entities after determining that one or more configuration settings of the instance satisfy a preference indicated in the request for the task, and that the retention period of the instance relative to a completion of an earlier task on the instance has not expired. A result of the task is stored.

Abstract: A reflector includes a reflector body having a slotted surface, a planar surface, and an ellipsoidal surface. The planar surface is opposite the slotted surface and is separated from the slotted surface by a thickness of the reflector body. The ellipsoidal surface is offset from the planar surface, is opposite the slotted surface and separated from the slotted surface by the thickness of the reflector body and spans the slotted surface of the reflector body. The ellipsoidal surface defines an elliptical profile that is orthogonal relative to the planar surface to concentrate heat flux at a distal focus of the elliptical profile using electromagnetic radiation reflected by the ellipsoidal surface of the reflector body. Semiconductor processing systems and material layer deposition methods are also described.

Abstract: Systems and methods are provided for recording video of a driver in a vehicle and a surrounding visual field of the driver. The system includes a detachable body coupled to a windshield of a vehicle. The system further includes three or more cameras coupled to the detachable body. The three or more cameras are configured to capture surrounding views from the detachable body. One of the three or more cameras faces a driver seat of the vehicle in response to the detachable body being coupled to the windshield of the vehicle. The video may be processed by the system, the cloud, or a combination of them.

Abstract: A method includes receiving from a client system a user input having input tokens and generating a span-based frame representation based on the input tokens. The span-based frame representation may include intents, slots, and a span. The span may include a first index endpoint associated with a first token and a second index endpoint associated with a second token. The method further includes encoding the user input, based on an encoder of a natural language understanding module, to generate a feature vector for the user input, and determining, by a length module of the natural language understanding module, a length of the span-based frame representation based on the feature vector for the user input. Generating the span-based frame representation may be further based on the length of the span-based frame representation. The method further includes, responsive to the user input, executing tasks based on the span-based frame representation.

Abstract: A memory includes a bitcell on a substrate, having a bitcell width and a bitcell height and a first access transistor and a second access transistor. The memory includes a first metal layer patterned to form a first pair of wordlines, including a first wordline coupled to a gate of the first access transistor and a second wordline coupled to a gate of the second access transistor. The memory includes a second metal layer patterned to form a pair of second metal layer islands. The pair of second metal layer islands include a first island coupled to the first wordline and a second island coupled to the second wordline. The memory includes a third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.

Abstract: In one embodiment, a method includes receiving a user input comprising input tokens from a client system, parsing the user input to determine ontology tokens and utterance tokens corresponding to the input tokens, decoding the ontology tokens and the utterance tokens to generate a span-based frame representation comprising intents, slots, and a span, wherein the ontology tokens are decoded into the intents and slots, and wherein the utterance tokens are decoded to determine the span comprising one or more tokens of the input tokens, wherein the span comprises a first index endpoint associated with a first token of the one or more tokens and a second index endpoint associated with a second token of the one or more tokens, and executing, responsive to the user input, one or more tasks based on the span-based frame representation.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

Abstract: A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

Abstract: A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: Reagents, methods, and kits for assaying enzymes associated with lysosomal storage diseases MPS-I, MPS-II, MPS-IIIA, MPS-IIIB, MPS-IVA, MPS-VI, and MPS VII.

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

Abstract: Reagents, methods, and kits for assaying enzymes associated with lysosomal storage diseases MPS-I, MPS-II, MPS-IIIA, MPS-IIIB, MPS-IVA, MPS-VI, and MPS VII.

Abstract: A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: A device may receive scenario data identifying a scenario for enterprise resource planning that includes a base solution and processes and may generate an output file based on the scenario data. The device may generate a hierarchy for the scenario based on the output file and may identify prerequisites for the scenario based on the output file. The device may generate configurations and test scripts for the scenario based on the hierarchy and the prerequisites and may retrieve, from a data structure associated with the device, master data associated with the configurations and the test scripts. The device may process the configurations, the test scripts, and the master data, with a machine learning model, to predict a risk severity associated with the scenario and may perform one or more actions based on the risk severity associated with the scenario.

Abstract: A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.