Abstract: A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph.

Abstract: A method and apparatus for performing template-based classification of a circuit design are disclosed. A template file is read that defines a plurality of channel-connected-region (CCR) templates. A graph is formatted for each of the CCR templates. A plurality of CCRs are identified based on a partitioned netlist file that defines a given circuit design. A graph is generated for each of the identified CCRs. A matching CCR template graph is identified for each generated CCR graph. The template file may further defines super-CCR templates, and a graph may be formatted for each of the super-CCR templates. All possible combinations of CCRs and previously-matched super-CCRs that are candidates to match the formatted super-CCR template graph may be determined in an interative manner, for each formatted super-CCR template graph. A determination may be made as to which of the candidate combinations actually match the formatted super-CCR template graph.

Abstract: A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.

Abstract: A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.

Abstract: A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog® is generated for the evaluate phase of a dynamic circuit. Second, “comment-logic” in Verilog® syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the “clk=0” and the “clk=1” conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art.

Abstract: A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog® is generated for the evaluate phase of a dynamic circuit. Second, “comment-logic” in Verilog® syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the “clk=0” and the “clk=1” conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art.

Abstract: A method for comparing two delimited strings, each of which has a plurality of substrings, includes pairing each substring in one of the delimited string with a corresponding substring in the other one of the delimited strings. The method further includes computing a proximity value for each pair of substrings, and computing a set of decaying weights corresponding to the pairs of substrings, multiplying the proximity value for each pair of substrings by the corresponding weight, and summing the weighted proximity values to obtain a strength of match between the delimited strings.

Abstract: A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.

Abstract: A method and system for providing artificial intelligence for planning and risk assessment of surgical paths to a tumor in an organ. The method and system achieve their objects related to path planning by providing a data-processing system programmed to do at least the following: define one or more risk-of-damage probability spaces within an organ, and, utilizing the defined risk-of-damage probability spaces, calculate an optimum path to the tumor in the organ. The definition of the risk-of-damage probability spaces can be done as follows: at least one functional region within an organ is defined; the defined functional region is subdivided into subregions; and a risk-of-damage probability is associated with each of the subregions such that a higher probability indicates a concomitant loss of function of the at least one functional area within the organ.

Abstract: A computer modulates among a number of states. Information stored in the computer memory includes predefined categories of an expected external stimulus. For example, the stimulus may include events and the categories include types of events. Also stored in memory are the predetermined states and likelihood functions for transitioning from one state to another. The states may represent emotional states, and the events represent emotion bearing events. Each type of event may have predefined emotional characteristics, with the likelihood functions being response to the occurrence of the events, the categorization of the events, and the characterization of the event's category.

Abstract: A method and implementing system are provided for handling detected faults in a processor to improve reliability of a computer system. An exemplary fault-tolerant on-line transactional (OLT) computer system is illustrated which includes first and second OLT processors connected to an I/O processor through a system bus. Transaction results are stored in local processor buffers and at predetermined batch intervals, the stored transactions are compared. The matched transaction results are flushed to data store while unmatched transactions are re-executed. If the same errors do not occur during a re-execution, the errors are determined to be transient and the transaction results are flushed to storage.

Abstract: A method and system for providing artificial intelligence for assessing a course of medical treatment. The method and system achieve their objects related to assessing a course of medical treatment by providing a data-processing system programmed to do at least the following: define a course of medical treatment, and calculate an assessment of the defined course of medical treatment. The defined course of medical treatment can include surgical intervention. Calculating the assessment of the defined course of medical treatment can include calculating the risks associated with surgical intervention. Calculating the risks associated with the surgical intervention can include defining surgical paths to a brain tumor and calculating the risks associated with the defined surgical paths to the brain tumor.

Abstract: Links in a network are switched between nodes in response to traffic and failure status of network links as follows. A total message time is calculated for a given network configuration. Nodes are identified having the most and the least messages. A new network configuration is considered, wherein a link from the minimum traffic nodes is reconfigured to the maximum traffic nodes. A maximum link and/or maximum connectivity rule are evaluated for the possible new configuration. If such a rule is not violated and the total message time is improved by the new configuration, the analysis is repeated for possible third, fourth, etc. configurations.

Abstract: A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.

Abstract: The present invention discloses a system and method to evaluate intrusive repair. The method and system is based on analyzing data from the field and drawing causal diagrams (cause-consequence diagrams). In an aspect of the present invention, a method and system for evaluating intrusive repair for a class of devices comprises providing a threshold time window for analyzing failure data. The system and method further includes utilizing a causal diagram based on the analysis of the failure data for the class of devices to indicate the probability of intrusive repair. In the present invention, two measures are defined to evaluate intrusive repair--intrusivability and one-fixability. Intrusivability is defined as the probability that a repair action will cause a new fault. One-fixability is defined as the probability that the diagnostic process will fix the fault on the first repair attempt. Both of these measures are determined by using the causal diagram in accordance with the present invention.

Abstract: A first set of test instructions are provided for a first node in a computer network. A corresponding second set is provided for a second node in the network. The test instruction sets are partitioned into modules. The nodes process their respective sets of test instructions independently to generate test results for each module on each node, except when a synchronizing event occurs. Each node stores its test results for each test module. Since the test modules have an ordered processing sequence, each node's test results for corresponding test modules can be compared asynchronously on an ongoing basis.

Abstract: A method and apparatus for determining the availability of a workstation in a distributed network. Availability is determined using an Availability Measurement System having a Downtime unit, an Availability Disable unit, and a Calculation unit. During the initialization of the workstation, a heartbeat monitor daemon is created to store, at predetermined time intervals, timestamps of the network. Once the workstation becomes unavailable, the recording of the timestamps ceases, thus, allowing an accurate representation of when the workstation became unavailable. Upon the return of the workstation to the status of available, the Downtime unit reads the current time of the network and the stored timestamp to calculate the duration of the unavailability of the workstation. The duration is then stored for later calculation of availability of the workstation for a defined interval of time using the Calculation unit.