Abstract: The present invention relates to the use of an immunogenic composition that comprises a porcine circovirus type 3 (PCV3) antigen for treatment of several clinical manifestations (diseases). Preferably, the clinical manifestations are associated with a PCV3 infection.

Abstract: The present invention relates to the use of an immunogenic composition that comprises a porcine circovirus type 3 (PCV3) antigen for treatment of several clinical manifestations (diseases). Preferably, the clinical manifestations are associated with a PCV3 infection.

Abstract: The present invention relates to the use of an immunogenic composition that comprises a porcine circovirus type 3 (PCV3) antigen for treatment of several clinical manifestations (diseases). Preferably, the clinical manifestations are associated with a PCV3 infection.

Abstract: The present invention relates to the use of an immunogenic composition that comprises a porcine circovirus type 3 (PCV3) antigen for treatment of several clinical manifestations (diseases). Preferably, the clinical manifestations are associated with a PCV3 infection.

Abstract: The present invention relates to the use of an immunogenic composition that comprises a porcine circovirus type 3 (PCV3) antigen for treatment of several clinical manifestations (diseases). Preferably, the clinical manifestations are associated with a PCV3 infection.

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Abstract: A plurality of heaters are disposed end to end within a bore hole of a formation where the bore hole extends from an upper end to a lower end such that a lower heater of the plurality of heaters is proximal to the lower end of the bore hole while every other of the plurality of heaters is distal from the lower end of the bore hole. Each of the plurality of heaters includes a fuel cell stack assembly having a plurality of fuel cells which convert chemical energy from a fuel into heat and electricity through a chemical reaction with an oxidizing agent. Each of the plurality of heaters has a thermal output that is less than or equal to a predetermined value except the lower heater of the plurality of heaters which has a thermal output that is greater than the predetermined value.

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Abstract: A plurality of heaters is provided to be disposed end to end within a bore hole of a formation where the bore hole extends from an upper end to a lower end such that a lower heater of the plurality of heaters is proximal to the lower end of the bore hole while every other of the plurality of heaters is distal from the lower end of the bore hole. Each of the plurality of heaters includes a fuel cell stack assembly having a plurality of fuel cells which convert chemical energy from a fuel into heat and electricity through a chemical reaction with an oxidizing agent. Each of the plurality of heaters has a thermal output that is less than or equal to a predetermined value except the lower heater of the plurality of heaters which has a thermal output that is greater than the predetermined value.

Abstract: A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-variation (OCV) margin from clock paths, removable OCV margin from data paths, removable IR drop margin from clock paths, and removable interconnects margin. At the timing analysis stage of a design flow, the method and apparatus determines the value of pessimism in the timing critical paths based on timing correlation between adjacent timing critical paths. In response to the determination, the value of pessimism may be reduced in the static timing analysis of the adjacent timing critical paths to optimize the timing performance of the integrated circuit at its desired clock frequency range.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: A method and apparatus for designing an integrated circuit to operate at a desired clock frequency range reduces process variation by estimating the value of removable pessimism from a static timing analysis. The pessimism includes, for example, at least one of the removable on-chip-variation (OCV) margin from clock paths, removable OCV margin from data paths, removable IR drop margin from clock paths, and removable interconnects margin. At the timing analysis stage of a design flow, the method and apparatus determines the value of pessimism in the timing critical paths based on timing correlation between adjacent timing critical paths. In response to the determination, the value of pessimism may be reduced in the static timing analysis of the adjacent timing critical paths to optimize the timing performance of the integrated circuit at its desired clock frequency range.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.