Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A system and device for reducing instantaneous voltage droop (IVD) during a scan shift operation is disclosed. In one embodiment, a system includes a first group of clock gating cells configured to receive an input clock signal and a first group of flip-flops coupled to the first group of clock gating cells. Each clock gating cell of the first group of clock gating cells includes a first delay element to delay the input clock signal by a first duration during a scan shift operation. The system also includes a second group of clock gating cells configured to receive the input clock signal, and a second group of flip-flops coupled to the second group of clock gating cells. Each clock gating cell of the second group of clock gating cells includes a second delay element to delay the input clock signal by a second duration during the scan shift operation.

Abstract: A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test output subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Abstract: A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test pattern subset from the tested circuit and provides a test system output that indicates a presence of any errors in functioning of the tested circuit.

Abstract: A method and apparatus are provided for analyzing test vectors for use in measuring static current consumed by an integrated circuit. A netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. Once the netlist has been read, cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. The nodes in the netlist that correspond to these pins are identified and are added to an list file. Once the list file has been generated, a computer simulation program is used to simulate a steady-state response of a functional model of the integrated circuit to a potential test vector and to output the resulting logic states on the nodes provided in the list file.

Abstract: A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).