Patents by Inventor Arun K. Malhotra

Arun K. Malhotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4769340
    Abstract: In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl.sub.3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10.sup.6 cycles.
    Type: Grant
    Filed: April 17, 1986
    Date of Patent: September 6, 1988
    Assignee: Exel Microelectronics, Inc.
    Inventors: Thomas T. L. Chang, Chun Ho, Arun K. Malhotra