Abstract: A device may include a core structure having low permeability characteristics and defining a first cross-sectional area, a coil member including one or more loops that winds around the core structure and defines a second cross-sectional area. The second cross-sectional area is between 1.2 to 5 times larger than the first cross-sectional area. The device may include a frame member positioned around the core structure or a portion thereof and the coil member may wind around the frame member to define the second cross-sectional area. The core structure may be composed of a low permeability magnetic material having a low relative permeability. The core structure may be composed of a high permeability magnetic material and the core structure may further include an air gap structure to enable the core structure to demonstrate the low permeability characteristics.

Abstract: A device includes a core structure including a first end plate and a second end plate. The first end plate and second end plate include a first portion and a second portion that extend from opposing sides of a third portion and include an increasing cross-sectional area configured to provide soft saturation properties in response to increasing electrical current. The core structure may further include a coil member and a core section. The core section is disposed between the first plate member and second plate member. The core section includes a first core member, a second core member, and a central disc member. The core section also includes a channel formed between the central disc member and the first core member and the second core member to enable the coil member to circumferentially wind around the central disc member.

Abstract: Systems, methods, techniques and apparatuses of a semiconductor control system are disclosed. One exemplary embodiment is a method for protecting a semiconductor switch comprising receiving a first voltage during a second blanking period following a first blanking period; determining whether a short circuit fault is occurring by comparing the first voltage to a fast detection threshold corresponding to a first value of a drain-source voltage of the semiconductor switch; if a short circuit is not occurring: receiving a second voltage after the second blanking period ends; determining whether a short circuit fault is occurring by comparing the second voltage to a slow detection threshold corresponding to a second value of the drain-source voltage; and if a short circuit fault is occurring, opening the semiconductor switch, wherein the first value of the drain-source voltage is greater than the second value of the drain-source voltage.

Abstract: Systems, methods, techniques and apparatuses of a semiconductor control system are disclosed. One exemplary embodiment is a method for protecting a semiconductor switch comprising receiving a first voltage during a second blanking period following a first blanking period; determining whether a short circuit fault is occurring by comparing the first voltage to a fast detection threshold corresponding to a first value of a drain-source voltage of the semiconductor switch; if a short circuit is not occurring: receiving a second voltage after the second blanking period ends; determining whether a short circuit fault is occurring by comparing the second voltage to a slow detection threshold corresponding to a second value of the drain-source voltage; and if a short circuit fault is occurring, opening the semiconductor switch, wherein the first value of the drain-source voltage is greater than the second value of the drain-source voltage.

Abstract: Unique systems, methods, techniques and apparatuses of semiconductor failure prognostication. One exemplary embodiment is a power converter comprising a semiconductor switch and a converter control system. The converter control system is configured to turn on the semiconductor switch, measure a first voltage and a current during reverse conduction, estimate junction temperature of the semiconductor device, turn off the semiconductor device, measure a second voltage after turning off the semiconductor device, determine a resistance value using the second voltage measurement, determine an expected resistance value, predict a failure of the semiconductor device using the resistance value and the expected resistance value, and transmit a semiconductor device failure warning.

Abstract: Unique systems, methods, techniques and apparatuses of semiconductor failure prognostication. One exemplary embodiment is a power converter comprising a semiconductor switch and a converter control system. The converter control system is configured to turn on the semiconductor switch, measure a first voltage and a current during reverse conduction, estimate junction temperature of the semiconductor device, turn off the semiconductor device, measure a second voltage after turning off the semiconductor device, determine a resistance value using the second voltage measurement, determine an expected resistance value, predict a failure of the semiconductor device using the resistance value and the expected resistance value, and transmit a semiconductor device failure warning.

Abstract: Unique systems, methods, techniques and apparatuses of a gate drive system are disclosed. One exemplary embodiment is a drive circuit electrically coupled to a main switching device including a first inverter, a first inverter controller, an air core transformer, at least one rectifier, at least two smoothing capacitors, a current buffer stage, and a detection circuit. The first inverter controller is structured to operate the first inverter in a first mode and a second mode. The air core transformer is structured to receive the converted AC power from the first inverter. The detection circuit is structured to detect a first mode of the first inverter and a second mode of the first inverter, and operate the current buffer stage based on a detected first mode of the inverter and a detected second mode of the first inverter.

Abstract: Unique systems, methods, techniques and apparatuses of a gate drive system are disclosed. One exemplary embodiment is a drive circuit electrically coupled to a main switching device comprising a first inverter, a first inverter controller, an air core transformer, at least one rectifier, at least two smoothing capacitors, a current buffer stage, and a detection circuit. The first inverter controller is structured to operate the first inverter in a first mode and a second mode. The air core transformer is structured to receive the converted AC power from the first inverter. The detection circuit is structured to detect a first mode of the first inverter and a second mode of the first inverter, and operate the current buffer stage based on a detected first mode of the inverter and a detected second mode of the first inverter.