Abstract: Disclosed are p53 peptidomimetic macrocycles, each p53 peptidomimetic macrocycle comprising an i, i+4 olefin staple and a polypeptide tail covalently linked to the p53 peptidomimetic macrocycle; an i, i+7 olefin staple and a polypeptide tail covalently linked to the p53 peptidomimetic macrocycle; or, an i, i+7 di-alkyne staple and optionally a polypeptide tail covalently linked to the p53 peptidomimetic macrocycle; wherein the p53 peptidomimetic macrocycle comprises all D-configuration amino acids and the polypeptide tail comprises three to nine amino acids, each amino acid of the polypeptide tail independently having a D-configuration or an L-configuration. The p53 peptidomimetic macrocycles are protease resistant, cell permeable without inducing membrane disruption, and intracellularly activate p53 by binding MDM2 and MDMX, thereby antagonizing MDM2 and MDMX binding to p53.

Abstract: The crosslinked peptidomimetic macrocycles disclosed herein comprise an alkene or alkyne staple and a poly-amino acid C-terminal tail. These crosslinked peptidomimetic macrocycles have improved binding to MDM2 and MDMX (aka MDM4), are protease resistant, cell permeable without inducing membrane disruption, and intracellularly activate p53 by binding MDM2 and MDMX thereby antagonizing MDM2 and MDMX binding to p53. These peptidomimetic macrocycles may be useful in anticancer therapies, particularly in combination with chemotherapy or radiation therapy.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: Techniques are disclosed relating to kernel task scheduling. In various embodiments, a computing device receives, at a first scheduler, a compute graph defining interrelationships for a set of tasks to be performed by the computing device. In some embodiment, the set of tasks are performed to provide an extended reality (XR) experience to a user. The first scheduler determines a schedule for implementing the set of tasks based on the interrelationships defined in the compute graph and issues instructions to cause a second scheduler of the computing device to schedule performance of the set of tasks in accordance with the determined schedule.

Abstract: A system including a first integrated circuit configured to render image data and transport the image data. Further, the system includes a second integrated circuit configured to receive the image data, determine whether the image data is missing data that was expected to have been received, and generate placeholder data in response to determining that the image data is missing data that was expected to have been received.

Abstract: First integrated circuitry including image data rendering circuitry configured to generate image data and memory configured to store a dashboard including dashboard entries indicating a state of the image data to the image data rendering circuitry, wherein the image data rendering circuitry is configured to operate based at least in part on feedback from the dashboard.

Abstract: An electronic device is provided that includes at least one image sensor for acquiring a video feed and one or more displays for presenting a passthrough video feed to a user. The electronic device can include a hierarchical failure detection scheme for detecting critical failures on the device. The hierarchical failure detection scheme may include monitoring a condition of a first subsystem with a second subsystem, monitoring a condition of the second subsystem with a third subsystem, monitoring a condition of the third subsystem with a fourth subsystem, and so on. The displays can operate in a first video passthrough mode or a second video passthrough mode based on the condition of the first subsystem as monitored by the second subsystem, the condition of the second subsystem as monitored by the third subsystem, and/or the condition of the third subsystem as monitored by the fourth subsystem.

Abstract: Aspects of the subject technology may provide time-synchronized image frames from multiple cameras to various system and/or application processes running on an electronic device. In one or more implementations, a frame identifier may be determined for each image frame from each camera based on a system pulse associated with the capture of the image frame. By generating frame identifiers based for images from multiple cameras based on a centralized source such as the system pulses, subsequent processes can immediately identify images from multiple cameras having the same frame identifier for co-processing of those images.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: An electronic device may include software and hardware subsystems that are centrally controlled by a user experience manager. The user experience manager can identify a current user context and enforce a corresponding power and performance policy for the various subsystems that is optimized for the current user context. The user experience manager can provide a set of restrictions at the launch of a user experience, can allow the various subsystems to vary their dynamic behavior based on current operating conditions as long as the dynamic adjustments do not violate the restrictions, and can perform a series of thermal mitigation operations as the internal temperature of the electronic device varies. The centralized user experience manager can also be configured to predict a user context based on monitored states of the subsystems and monitored application usage on the electronic device.

Abstract: A head-mounted device is provided that includes one or more cameras configured to acquire a raw video feed and one or more displays configured to present a passthrough video feed to a user. Generation of the passthrough video feed can involve processing the raw video feed using an image signal processor and auxiliary compute blocks. One or more of the auxiliary compute blocks can be bypassed in response to detecting one or more failures associated with the auxiliary compute blocks. Configured and operated in this way, the head-mounted device can fall back to a more reliable passthrough video feed without having to power cycle the head-mounted device when a failure occurs.

Abstract: A request to transition a computing system from a first state to a second state is received, and a respective manifest is compiled for each of a plurality of processors of the computing system. Each manifest comprises a transition identifier representing a command to transition from the first state to the second state and an action time for executing one or more operations associated with the transition identifier. The respective manifests are dispatched to the plurality of processors, and status reports are received from the plurality of processors regarding the transition from the first state to the second state.

Abstract: This disclosure relates to a method, article of manufacture, and apparatus for updating a Java management extensions (JMX) collector. In some embodiments, this includes monitoring the output of a JMX provider details for a cloud computing platform. MBean tree structures from the cloud computing platform are analyzed. If changes in an MBean tree structure are detected, a revised JMX collector data file is prepared. If the revised JMX collector data file is determined to be different than an installed JMX collector data file, the installed JMX collector data file is backed up and replaced with the revised JMX collector data file. Data from the cloud computing platform is stored in a computer memory using configuration settings from the revised JMX collector data file.