Abstract: A controller area network (CAN) node is described for determining a bus load on a CAN bus. An indication of a time window duration of a time window is received by the CAN node and a start time for determining a bus load and an end time based on the start time and the time window duration is defined. The bus load is based on determining whether the CAN bus is active for each bit of one or more bits detected on the CAN bus between the start time and the end time. The bus load is compared to a threshold range. A signal is sent to a host processor if the bus load exceeds or falls below the threshold range.

Abstract: A virtualized controller area network (CAN) system including multiple virtual CAN controllers and a CAN virtual network controller. The CAN virtual network controller includes virtual CAN interfaces, network interfaces, and a configuration controller. Each of the virtual CAN interfaces communicatively links each virtual CAN controller with the network interfaces, which are each configured to communicatively link one or more of virtual CAN controllers into a CAN network. The configuration controller programs any one or more of the network interfaces to communicatively link any one or more of the virtual CAN controllers in each of one or more CAN networks. The configuration controller configures a network interface for virtual communications for implementing a virtual CAN network, or enables a linked physical protocol engine for implementing a physical CAN network. The number of protocol engines needed, if any, may be significantly reduced thereby reducing pin count and silicon area consumption.

Abstract: A controller area network (CAN) node is described for determining a bus load on a CAN bus. An indication of a time window duration of a time window is received by the CAN node and a start time for determining a bus load and an end time based on the start time and the time window duration is defined. The bus load is based on determining whether the CAN bus is active for each bit of one or more bits detected on the CAN bus between the start time and the end time. The bus load is compared to a threshold range. A signal is sent to a host processor if the bus load exceeds or falls below the threshold range.

Abstract: A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.

Abstract: A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.

Abstract: A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.