Abstract: An example apparatus includes: first voltage-to-delay circuitry having an output; second voltage-to-delay circuitry having an output; time domain converter circuitry having a first input, a trim input, and an output, the first input of the time domain converter circuitry coupled to the first voltage-to-delay circuitry; comparator circuitry having a first input, a second input, and an output, the first input of the comparator circuitry coupled to the output of the first voltage-to-delay circuitry and the first input of the time domain converter circuitry, the second input of the comparator circuitry coupled to the output of the second voltage-to-delay circuitry; and trim circuitry having a first input, a second input, and an output, the first input of the trim circuitry coupled to the output of the time domain converter circuitry, the second input of the trim circuitry coupled to the output of the comparator circuitry.

Abstract: Methods, apparatus, and systems are described to facilitate phase detection for data clock synchronization. An example phase detection circuit includes a first switch including a control terminal, the control terminal of the first switch coupled to a clock generator; a second switch including a control terminal, the control terminal of the second switch coupled to the clock generator; a first capacitor including a first terminal, the first terminal of the first capacitor coupled to a second terminal of the first switch; a second capacitor including a first terminal, the first terminal of the second capacitor coupled to a second terminal of the second switch; and a comparator including a first input terminal and a second input terminal, the first input terminal of the comparator coupled to the second terminal of the first switch, the second input terminal of the comparator coupled to the second terminal of the second switch.

Abstract: A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.

Abstract: Tissue adjustment implants useful for adjusting a position of tissue in a patient are described. In an embodiment, a tissue adjustment implant includes a main body having a series of outwardly-extending projections. The tissue adjustment implants can be used in a variety of treatments, such as in the treatment of Obstructive Sleep Apnea and snoring.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: In a system and method for determining guide points or a guide path for display on an endoscopic display, image data corresponding to a surgical treatment site is captured using a camera. Using the image data, the positions of one or more reference points within the surgical environment, are determined. Based on the positions of the reference points, the positions of guide points spaced from the reference point are estimated or determined, in some cases using predetermined offsets. The guide points or guide path is displayed as an overlay of the image data on an image display. In an embodiment using the system for a sleeve gastrectomy procedure, the reference points are input by a user or determined by the system with reference to a bougie that has been positioned within a stomach at the operative site, and the guide path is used as a guide for stapling and resection to form the sleeve.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: Tissue adjustment implants useful for adjusting a position of tissue in a patient are described. In an embodiment, a tissue adjustment implant includes a main body having a series of outwardly-extending projections. The tissue adjustment implants can be used in a variety of treatments, such as in the treatment of Obstructive Sleep Apnea and snoring.

Abstract: Tissue adjustment implants useful for adjusting a position of tissue in a patient are described. In an embodiment, a tissue adjustment implant includes a main body having a series of outwardly-extending projections. The tissue adjustment implants can be used in a variety of treatments, such as in the treatment of Obstructive Sleep Apnea and snoring.

Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.

Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.

Abstract: Devices, kits, and methods useful in the treatment of Obstructive Sleep Apnea (OSA) are described. Example devices include a jig, a first needle, a second needle, and a third needle. An example jig comprises a drill guide and a tongue depressor. A first needle comprises an elongate shaft that defines a bend and a curve. A second needle comprises an elongate shaft that defines a curve. A third needle comprises an elongate shaft that defines a curve.

Abstract: Devices, kits, and methods useful in the treatment of Obstructive Sleep Apnea (OSA) are described. Example devices include a jig, a first needle, a second needle, and a third needle. An example jig comprises a drill guide and a tongue depressor. A first needle comprises an elongate shaft that defines a bend and a curve. A second needle comprises an elongate shaft that defines a curve. A third needle comprises an elongate shaft that defines a curve.