Patents by Inventor Arun Patel

Arun Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11736511
    Abstract: Information technology/cyber security for computer-related processes in which vulnerabilities are identified and, those vulnerabilities which are technology-related are automatically remediated by determining and executing network-based tasks. The most granular level of computer-related process assessment in made possible by reliance on a critical function/process taxonomy this is automatically generated and, as such, the present invention, identifies both technology and non-technology-related vulnerabilities.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 22, 2023
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Casey L. Flaherty, Michael Sbandi, Jo-Ann Taylor, Michael Robert Young, Zarna Arun Patel
  • Publication number: 20230140547
    Abstract: A system includes a programmable logic fabric core of an integrated circuit device and an IO interface communicatively coupled to the programmable logic fabric core. The IO interface includes multiple IO banks to implement a memory channel. Each IO bank includes a memory controller to control memory accesses of a memory device over the memory channel and multiple physical layer and IOs circuits to provide connections between the memory controller and the memory device. The respective memory controller may receive only a portion of data to be sent over the memory channel or multiple memory controllers may each receive all data to be sent over the memory channel.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 4, 2023
    Inventors: Terence Magee, Jeffrey Schulz, Arun Patel
  • Publication number: 20220115047
    Abstract: An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: Intel Corporation
    Inventors: Archanna Srinivasan, Arvind Tirumalai, Arch Zaliznyak, Gopal Iyer, Hon Khet Chuah, Arun Patel, Kok Kee Looi
  • Publication number: 20220030025
    Abstract: Information technology/cyber security for computer-related processes in which vulnerabilities are identified and, those vulnerabilities which are technology-related are automatically remediated by determining and executing network-based tasks. The most granular level of computer-related process assessment in made possible by reliance on a critical function/process taxonomy this is automatically generated and, as such, the present invention, identifies both technology and non-technology-related vulnerabilities.
    Type: Application
    Filed: October 8, 2021
    Publication date: January 27, 2022
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Casey L. Flaherty, Michael Sbandi, Jo-Ann Taylor, Michael Robert Young, Zarna Arun Patel
  • Patent number: 11184384
    Abstract: Information technology/cyber security for computer-related processes in which vulnerabilities are identified and, those vulnerabilities which are technology-related are automatically remediated by determining and executing network-based tasks. The most granular level of computer-related process assessment in made possible by reliance on a critical function/process taxonomy this is automatically generated and, as such, the present invention, identifies both technology and non-technology-related vulnerabilities.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: November 23, 2021
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Casey L. Flaherty, Michael Sbandi, Jo-Ann Taylor, Michael Robert Young, Zarna Arun Patel
  • Publication number: 20200396240
    Abstract: Information technology/cyber security for computer-related processes in which vulnerabilities are identified and, those vulnerabilities which are technology-related are automatically remediated by determining and executing network-based tasks. The most granular level of computer-related process assessment in made possible by reliance on a critical function/process taxonomy this is automatically generated and, as such, the present invention, identifies both technology and non-technology-related vulnerabilities.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Casey L. Flaherty, Michael Sbandi, Jo-Ann Taylor, Michael Robert Young, Zarna Arun Patel
  • Publication number: 20080193529
    Abstract: Dipeptidylpeptidase IV inhibitor (herein referred to as DPP-IV) that may be 98.5-100% pure is a high-dose drug capable of being directly compressed with a glitazone and specific excipients into sold form dosage forms, such as tablets and capsules having desired, hardness, disintegrating ability and acceptable dissolution characteristics. DPP-IV is not inherently compressible and thus presents formulation problems. Excipients used in the formulation enhance the flow and compaction properties of the drug and tableting mix. Optimal flow contributes to uniform die fill and weight control. The binder used ensures sufficient cohesive properties that allow DPP-IV to be compressed using the direct compression method. The tablets produced provide an acceptable in vitro dissolution profile.
    Type: Application
    Filed: June 8, 2006
    Publication date: August 14, 2008
    Inventors: James Kowalski, Jay Parthiban Lakshman, Arun Patel
  • Publication number: 20080092146
    Abstract: An architecture for a scalable computing machine built using configurable processing elements, such as FPGAs, is provided. The machine can enable implementation of large scale computing applications using a heterogeneous combination of hardware accelerators and embedded microprocessors spread across many FPGAs, all interconnected by a flexible communication network structure.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 17, 2008
    Inventors: Paul Chow, Christopher Madill, Arun Patel, Manuel Saldana De Fuentes
  • Publication number: 20060159754
    Abstract: The present invention is directed to solid, sustained-release, oral dosage form pharmaceutical compositions which contain therapeutic amounts of a pharmaceutically active agent, hydroxypropyl methyl cellulose and a non-ionic, hydrophilic polymer selected from the group consisting of hydroxyethyl cellulose having a number average molecular weight ranging from 90,000 to 1,300,000, hydroxypropyl cellulose having a number average molecular weight of 370,000 to 1,500,000, and poly(ethylene oxide) having a number average molecular weight ranging from 100,000 to 500,000.
    Type: Application
    Filed: March 21, 2006
    Publication date: July 20, 2006
    Inventors: Rajen Shah, Arun Patel, Roy Sandry
  • Patent number: 6590469
    Abstract: A high frequency, large bandwidth electronic device for transforming balanced/unbalanced electrical signals. In one embodiment, the device comprises an auto-transformer mounted on substrate interposed between the balanced and unbalanced port so as minimize parasitic losses. Bonded bi-filar wire is wound around the auto-transformer core which facilitates a low, balanced leakage inductance thereby further enhancing device bandwidth. A method of manufacturing the aforementioned electronic device is also disclosed.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: July 8, 2003
    Assignee: Pulse Engineering, Inc.
    Inventor: Arun Patel
  • Patent number: 5227297
    Abstract: A tripeptide ligand of the formula -X-Y-Argininal is used to purify plasminogen activators.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: July 13, 1993
    Assignee: SmithKline Beecham Corporation
    Inventors: Arun Patel, A. Hirotoshi Nishikawa
  • Patent number: 5141862
    Abstract: A method for purifying tPA or a plasminogen activator having an active site resembling that of tPA from an impure solution thereof which comprises contacting the impure solution with a solid support having bound thereto a tripeptide of the formula: -X-Y-argininal, wherein X and Y are amino acids selected from the group consisting of pro, phe, trp and tyr. The method is also used with a tripeptide of the formula: -phe-Y-argininal, wherein Y is selected from the group consisting of phe, pro, trp, tyr, val, ile and glu(PEA).
    Type: Grant
    Filed: April 17, 1990
    Date of Patent: August 25, 1992
    Assignee: SmithKline Beecham Corporation
    Inventors: Arun Patel, A. Hirotoshi Nishikawa