Patents by Inventor Arun Prakash JANA
Arun Prakash JANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250117332Abstract: A data storage controller is provided that includes: a computer-readable storage medium storing one or more sequences of instructions; and one or more processors configured to execute the one or more sequences of instructions to: receive a host write request for a logical drive corresponding to a redundant array of physical drives, wherein the redundant array of physical drives comprises a first physical drive of a first drive type and a second physical drive of a second drive type different from the first drive type, and wherein data stored on the first physical drive is mirrored on the second physical drive; generate and issue a first input-output (IO) request for the first physical drive based on the host write request and a first cache policy associated with the first drive type; and generate and issue a second IO request for the second physical drive based on the host write request and a second cache policy associated with the second drive type, wherein the first cache policy is different from the secondType: ApplicationFiled: October 4, 2023Publication date: April 10, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash Jana
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Patent number: 12271316Abstract: A memory system includes a firmware unit and a cache module that includes a cache controller and a cache memory. The cache controller receives an I/O message that includes a local message ID (LMID) and data to be written to a logical drive (LD), stores the data in a cache segment (CS) row of the cache memory and sends an ID of the CS row to the firmware unit. The firmware unit, in response to receiving the ID of the CS row, acquires a timestamp and stores the timestamp to check against a cache flush timeout for the CS row. The firmware unit periodically checks cache flush timeout and in response to detecting the cache flush timeout, sends a flush command with the ID of the CS row to the cache controller. The cache controller, in response to receiving the flush command, flushes the first data of the CS row.Type: GrantFiled: February 16, 2023Date of Patent: April 8, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash Jana
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Publication number: 20250085900Abstract: A method may include receiving, by one or more controllers, a segment of data to write to a logical device, the logical device having a plurality of physical disks. The method may include causing, by the one or more controllers, to store a first plurality of contiguous data strips of the segment of data on a first physical disk of the plurality of the physical disks up to a first threshold. In response to reaching the first threshold, a second plurality of contiguous data strips of the segment of data can be stored on a second physical disk of the plurality of the physical disks, the second plurality of contiguous data strips following sequentially after the first plurality of contiguous data strips. The method may include splitting of the segment of data into the first plurality of contiguous data strips and the second plurality of contiguous data strips.Type: ApplicationFiled: September 12, 2023Publication date: March 13, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash Jana
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Publication number: 20250077319Abstract: A device in communication with a plurality of memory devices storing a plurality of datasets and a host, the device including one or more circuits to receive a plurality of messages pertaining to the plurality of datasets, determine an amount of information corresponding to each dataset of the plurality of datasets, identify actions for each message of the plurality of messages, the actions including at least one of updates to the plurality of datasets or accesses of the plurality of datasets, update a table to reflect receipt of the plurality of messages, and determine a pattern associated with the plurality of messages.Type: ApplicationFiled: August 29, 2023Publication date: March 6, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash Jana
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Patent number: 12242409Abstract: Systems and methods of communicating use device level throttling. Some embodiments relate to a method of communicating in a network. The systems and methods can provide a first communication associated with a device for issuance, issue the first communication if a queue depth value for the device is less than an issued communication value, and listing the first communication on a pend list for the device if a queue depth value for the device is less than the issued communication value.Type: GrantFiled: October 18, 2022Date of Patent: March 4, 2025Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Arun Prakash Jana
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Publication number: 20250068350Abstract: A device including one or more circuits. The one or more circuits can receive a request associated with a first dataset stored by a memory device of a plurality of memory devices. The one or more circuits can generate, based on information associated with the memory device and the request, a first value corresponding to a first portion of a first map. The one or more circuits can determine, based on a first value of the first portion of the first map, that a first row of the plurality of rows includes a bad block.Type: ApplicationFiled: August 22, 2023Publication date: February 27, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Arun Prakash Jana, Sumalatha Kori
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Publication number: 20250036290Abstract: A system may include one or more processors configured to receive a write operation to write a block of data to a logical device established using one or more storage devices which reserve one or more data strips and one or more metadata blocks to store data of write journals. The one or more processors may identify a first data strip of the block of data to be written to a first storage device of the one or more storage devices, write a copy of the first data strip to a data strip of the one or more data strips reserved on the first storage device, write metadata relating to the block of data to a metadata block of the one or more metadata blocks reserved on the first storage device, and execute the write operation to store the block of data across the one or more storage devices.Type: ApplicationFiled: July 28, 2023Publication date: January 30, 2025Applicant: Avago Technologies International Sales Pte. LimitedInventors: Amar Deep Kumar, Arun Prakash Jana
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Patent number: 12169650Abstract: A system may include one or more processors configured to receive a frame comprising a quantity of commands, a quantity of storage devices, and a buffer map. In response to the frame, the one or more processors may read, using the buffer map and from a memory, (1) input data for each of one or more storage devices corresponding to the quantity of storage devices and (2) an identifier of each of the one or more storage devices. The one or more processors may send, to the one or more storage devices, a plurality of commands corresponding to the quantity of commands, based at least on the input data for each storage device and the identifier of each storage device.Type: GrantFiled: July 28, 2023Date of Patent: December 17, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Arun Prakash Jana, Amar Deep Kumar
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Publication number: 20240281380Abstract: A memory system includes a firmware unit and a cache module that includes a cache controller and a cache memory. The cache controller receives an I/O message that includes a local message ID (LMID) and data to be written to a logical drive (LD), stores the data in a cache segment (CS) row of the cache memory and sends an ID of the CS row to the firmware unit. The firmware unit, in response to receiving the ID of the CS row, acquires a timestamp and stores the timestamp to check against a cache flush timeout for the CS row. The firmware unit periodically checks cache flush timeout and in response to detecting the cache flush timeout, sends a flush command with the ID of the CS row to the cache controller. The cache controller, in response to receiving the flush command, flushes the first data of the CS row.Type: ApplicationFiled: February 16, 2023Publication date: August 22, 2024Inventor: Arun Prakash Jana
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Publication number: 20240126713Abstract: Systems and methods of communicating use device level throttling. Some embodiments relate to a method of communicating in a network. The systems and methods can provide a first communication associated with a device for issuance, issue the first communication if a queue depth value for the device is less than an issued communication value, and listing the first communication on a pend list for the device if a queue depth value for the device is less than the issued communication value.Type: ApplicationFiled: October 18, 2022Publication date: April 18, 2024Applicant: Avago Technologies International Sales Pte. LimitedInventor: Arun Prakash JANA