Abstract: A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Abstract: A serial data channel includes a transmitter that encodes serial data using a quaternary PAM-4 scheme, wherein the four PAM-4 signal levels include two balanced pairs of differential signal levels. The channel includes a de-emphasis circuit that determines that first and second symbols are in a first PAM-4 state, that a third symbol is in a second PAM-4 state, and provides a first de-emphasis to a voltage level of the second symbol in response to determining that the third symbol is represented as the second state. The de-emphasis circuit further determines that fourth and fifth symbols are in the second state, that a sixth symbol is in the first state, and provides a second de-emphasis to a voltage level of the fifth symbol in response to determining that the sixth symbol is represented as the first state. The first de-emphasis and the second de-emphasis represent different de-emphasis levels.

Abstract: An information handling system communicates information across a physical link with high and low signal values sent at a unit interval. Feed forward equalization improves signal transfer with pre-emphasis of low-to-high signals and de-emphasis of high-to-low signals lasting for a fraction of the unit interval, such as one-half or one-quarter of the unit interval. Fractional unit interval pre-emphasis and de-emphasis reduce inter symbol interference to improve frequency domain eye structure at the physical link receiver.

Abstract: A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Abstract: An information handling system communicates information across a physical link with high and low signal values sent at a unit interval. Feed forward equalization improves signal transfer with pre-emphasis of low-to-high signals and de-emphasis of high-to-low signals lasting for a fraction of the unit interval, such as one-half or one-quarter of the unit interval. Fractional unit interval pre-emphasis and de-emphasis reduce inter symbol interference to improve frequency domain eye structure at the physical link receiver.

Abstract: A high-speed serial data interface includes a transmitter and a receiver. The transmitter includes a feed-forward equalization (FFE) module. The FFE module has a main tap and at least one secondary tap. In a first mode, a sum of absolute values of a main tap compensation value and a secondary tap compensation value of each one of the at least one secondary tap is equal to one. In a second mode, the main tap compensation value has a unity gain equal to one, and each secondary tap compensation value is greater than or equal to the secondary tap compensation value in the first mode divided by the main tap compensation value in the first mode.

Abstract: A method includes providing a first circuit trace and a second circuit trace on a printed circuit board, determining a far end cross-talk (FEXT) response associated with the first circuit trace, determining a time delay associated with the second circuit trace, estimating a floquet response associated with the time delay, comparing the FEXT response with an interface frequency associated with the first circuit trace, comparing the floquet response with the interface frequency, and determining whether the floquet response cancels the FEXT response on the first circuit trace at the interface frequency.

Abstract: A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ? t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

Abstract: A method includes providing a first circuit trace and a second circuit trace on a printed circuit board, determining a far end cross-talk (FEXT) response associated with the first circuit trace, determining a time delay associated with the second circuit trace, estimating a floquet response associated with the time delay, comparing the FEXT response with an interface frequency associated with the first circuit trace, comparing the floquet response with the interface frequency, and determining whether the floquet response cancels the FEXT response on the first circuit trace at the interface frequency.

Abstract: A method includes receiving a serial data stream at a transmitter of a serial channel, encoding the serial data stream using a quaternary pulse amplitude modulation (PAM-4) scheme into a stream of 2-bit symbols, wherein a particular symbol is represented as a signal at one of four signal levels provided for a unit interval of time, determining that a first symbol of the encoded serial data stream is represented as a highest state of the PAM-4 scheme, and, in response, providing a first output signal on an output of the transmitter, wherein the first output signal includes a first portion at a first voltage level associated with the highest state for a first half of a first unit interval of time associated with the first symbol, followed by a second portion at a second voltage level associated with a de-emphasized highest state of the PAM-4 scheme for a second half of the first unit interval of time.

Abstract: A serial data channel includes a transmitter that encodes data using a PAM-4 where each symbol is represented by one of four signal levels comprising two balanced pairs of differential signal levels, and a de-emphasis circuit. The circuit determines that a symbol represents as a first instance of a first signal state, determines that a next symbol represents a second instance of the first state, and determines that a third symbol is represented as a second state. The circuit determines that the second state is of a same balanced pair as the first state and, in response, provides a de-emphasis to the second symbol. The circuit determines that the second state is of a different balanced pair as the first state and, in response, provides the de-emphasis and a correction factor to the second symbol.

Abstract: A method includes receiving a serial data stream at a transmitter of a serial channel, encoding the serial data stream using a quaternary pulse amplitude modulation (PAM-4) scheme into a stream of 2-bit symbols, wherein a particular symbol is represented as a signal at one of four signal levels provided for a unit interval of time, determining that a first symbol of the encoded serial data stream is represented as a highest state of the PAM-4 scheme, and, in response, providing a first output signal on an output of the transmitter, wherein the first output signal includes a first portion at a first voltage level associated with the highest state for a first half of a first unit interval of time associated with the first symbol, followed by a second portion at a second voltage level associated with a de-emphasized highest state of the PAM-4 scheme for a second half of the first unit interval of time.

Abstract: A trace route including a first signal route to couple a first signal transmitter to a first signal receiver. The first signal route including a first signal route section coupled to the transmitter and configured in a first zig-zag pattern, the first zig-zag pattern including a first unit cell having a first unit cell length, and a second signal route section connected to the first signal route section and coupled to the receiver, and configured in a second zig-zag pattern, the second zig-zag pattern comprising a second unit cell having a second unit cell length, the first unit cell length is less than the second unit cell length.

Abstract: A trace route including a first signal route to couple a first signal transmitter to a first signal receiver. The first signal route including a first signal route section coupled to the transmitter and configured in a first zig-zag pattern, the first zig-zag pattern including a first unit cell having a first unit cell length, and a second signal route section connected to the first signal route section and coupled to the receiver, and configured in a second zig-zag pattern, the second zig-zag pattern comprising a second unit cell having a second unit cell length, the first unit cell length is less than the second unit cell length.

Abstract: A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ? t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

Abstract: A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ? ? t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

Abstract: A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ? t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.