Patents by Inventor Arun Ramakrishnan

Arun Ramakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120173535
    Abstract: Techniques provided for allowing external access by other users to private information that is maintained on local storage of a computer and owned by an information owner. The private information is uploaded from the local storage to an externally accessible information source that is accessible by the other users. A request from a user to access the private information is received by the owner, who determines whether to allow access the private information. If so, the owner sends a private information sharing authorization to a collaboration orchestrator, which retrieves the private information from the external source and provides the private information to the user. The owner optionally requests to collaborate with the user before deciding whether to allow access to the private information. One or both of the identities of the owner and user can remain anonymous until agreeing on revealing identities. A system and program product is also provided.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arun Ramakrishnan, Rohit Shetty
  • Publication number: 20110277618
    Abstract: A method and apparatus for fabricating microbraided structures is provided. A microbraiding device includes first and second carrier members that are movable with respect to each other. Each carrier includes a plurality of shelters. Spool-less strands of microfiber are retained in shuttles that are movable between the first and second shelters under magnetic forces. The microbraid structure is fabricated as the shuttles move between the first shelters, and as the first carrier member moves relative to the second carrier member.
    Type: Application
    Filed: November 19, 2009
    Publication date: November 17, 2011
    Applicants: Philadelphia Health & Education Corporation d/b/a Drexel University College of Medicine, DREXEL UNIVERSITY
    Inventors: Simon Giszter, Tae Gyo Kim, Arun Ramakrishnan
  • Publication number: 20110145313
    Abstract: A method and system for transport data compression between a server and a client based on patches to the dictionaries used for encoding the data. The method includes requesting the server for data, returning the data and a dictionary patch to the client where data having been compressed based on a previously used dictionary and the dictionary patch, and decompressing the returned data using the dictionary and the dictionary patch. The dictionary patch includes updates to the previously used dictionary. Each dictionary has a dictionary identifier that the server and client use to identify the dictionary in their requests and responses. The identifier might be a unique identification or a network session number. Upon receiving a response, the client updates the previously used dictionary with information in the patch and decompresses the returned data using the updated dictionary.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: International Business Machines Corporation
    Inventors: Hariharan L. Narayanan, Arun Ramakrishnan, Krishna C. Shastry, Rohit Shetty
  • Publication number: 20110082883
    Abstract: A method, system and computer program product is disclosed for intelligent data mining. The method comprises receiving an event from an application, assigning property weights to properties of the event, and building a query from these properties based on the property weights. The method further comprises assigning search engine weights to a group of search engines, selecting at least some of the search engines based on the search engine weights, and sending the built query to the selected search engines. Results from the selected search engines are stored in a knowledge repository and used to adjust the property weights and the search engine weights. The invention may be used to provide an analysis with information about a problem, and to manage a solutions database which can be used for problem determination. The invention provides a low cost solution for collecting relevant information from online sources.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: International Business Machines Corporation
    Inventors: Hariharan L. Narayanan, Arun Ramakrishnan, Krishna C. Shastry, Rohit Shetty
  • Publication number: 20100100369
    Abstract: A dictionary mapping source locale strings to target locale strings is constructed. A tree is constructed from the dictionary. The tree has nodes including a start node, end nodes, and string nodes. The nodes form node chains of the tree that correspond to the source locale strings. Each node chain links a collection of the nodes from the start node to a string node. Each node other than the start node has a parent node and corresponds to a character of the source locale strings. Each node other than the end nodes has one or more child nodes. Each string node ends a node chain, and corresponds to a mapping within the dictionary of a source locale string to a target locale string. An input string having the source locale is processed against the tree to generate an output string having the target locale.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 22, 2010
    Applicant: International Business Machines Corporation
    Inventors: Rohit Shetty, Arun Ramakrishnan, Saurabh Dravid, Krishna Shastry
  • Patent number: 7319272
    Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: January 15, 2008
    Assignee: LSI Logic Corporation
    Inventors: Arun Ramakrishnan, Farshad Ghahghahi, Aritharan Thurairajaratnam, Leah M. Miller
  • Publication number: 20060223341
    Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 5, 2006
    Inventors: Arun Ramakrishnan, Farshad Ghahghahi, Aritharan Thurairajaratnam, Leah Miller
  • Patent number: 7105926
    Abstract: A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: September 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Arun Ramakrishnan, Anand Govind, Farshad Ghahghahi
  • Patent number: 7095107
    Abstract: The present disclosure is directed to ball assignment schemes for ball grid array packages in integrated circuits with increased signal count. The ball assignment scheme includes an array of electrical contacts. The array has a first diagonal including a pair of signal contacts adjacent to a pair of first-type voltage supply contacts. The array further includes a crossing diagonal having a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 22, 2006
    Assignee: LSI Logic Corporation
    Inventors: Arun Ramakrishnan, Anand Govind
  • Publication number: 20060118929
    Abstract: The present disclosure is directed to ball assignment schemes for ball grid array packages in integrated circuits with increased signal count. The ball assignment scheme includes an array of electrical contacts. The array has a first diagonal including a pair of signal contacts adjacent to a pair of first-type voltage supply contacts. The array further includes a crossing diagonal having a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.
    Type: Application
    Filed: December 7, 2004
    Publication date: June 8, 2006
    Applicant: LSI Logic Corporation
    Inventors: Arun Ramakrishnan, Anand Govind
  • Patent number: 6971081
    Abstract: A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: November 29, 2005
    Assignee: LSI Logic Corporation
    Inventor: Arun Ramakrishnan
  • Publication number: 20050110167
    Abstract: A flip chip substrate is provided, which includes a plurality of conductive layers, including a top layer and a bottom layer. A first plurality of contacts, including first and second contacts corresponding to a differential signal pair, are arranged on the top layer within a die bonding area. A second plurality of contacts, including third and fourth contacts corresponding to the differential signal pair, are arranged on the bottom layer. First and second traces are routed between the first and third contacts and between the second and fourth contacts, respectively, wherein the second trace is routed out of the die bonding area on a different layer than the first trace. The traces are routed in a manner that reduces the length difference between the traces.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 26, 2005
    Applicant: LSI Logic Corporation
    Inventors: Arun Ramakrishnan, Anand Govind, Farshad Ghahghahi
  • Publication number: 20050071799
    Abstract: A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Inventor: Arun Ramakrishnan
  • Patent number: 6828682
    Abstract: A substrate that includes a non-electrically conductive core having a first side and an opposing second side. A first electrically conductive layer is disposed on the first side of the core, and a second electrically conductive layer is disposed on the second side of the core. Electrically conductive core vias extend from the first side of the core to the second side of the core. The core vias are disposed in an array. An electrically conductive contact is formed on an upper build-up layer on the first side of the core, and overlies the array of core vias. A first electrically conductive via electrically connects the contact to an intervening build-up layer disposed between the upper build-up layer and the first electrically conductive layer. The first via overlies the core via array. A second electrically conductive via electrically connects the intervening build-up layer and the first electrically conductive layer, where the second electrically conductive via is not disposed over the core via array.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: December 7, 2004
    Assignee: LSI Logic Corporation
    Inventor: Arun Ramakrishnan