Patents by Inventor Arun S. Athreya

Arun S. Athreya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240354209
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Patent number: 12099420
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: September 24, 2024
    Assignee: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Patent number: 11145389
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Arun S. Athreya, Venkata S. Surampudi
  • Publication number: 20210141703
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Naveen Vittal Prabhu, Aliasgar Madraswala, Rohit Shenoy, Shankar Natarajan, Arun S. Athreya
  • Patent number: 10650886
    Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
  • Publication number: 20200105363
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Arun S. Athreya, Venkata S. Surampudi
  • Publication number: 20190267080
    Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
    Type: Application
    Filed: February 28, 2019
    Publication date: August 29, 2019
    Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
  • Patent number: 10229735
    Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
  • Publication number: 20170364275
    Abstract: Technologies for managing end of life behavior of a storage device include an apparatus that includes a memory that includes a plurality of storage cells and a controller to manage read and write operations of the memory. The controller is to determine whether the memory is presently operated in a read-only mode due to a presence of an end of life condition, determine, in response to a determination that the memory is presently operated in the read-only mode and in response to an action of a host, whether to transition the memory to a temporary write mode, and transition, in response to a determination to transition the memory to a temporary write mode, the memory to the temporary write mode. Other embodiments are described and claimed.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Shankar Natarajan, Arun S. Athreya, Sanjeev N. Trika