Patents by Inventor Arun Sankar

Arun Sankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Maintaining files in a retained file system
    Patent number: 10585762
    Abstract: To maintain files in a retained file system, a run-time error detection code (EDC) is generated for a retained file. The run-time EDC is generated on the basis of at least one of entire content and metadata of the retained file. Further, the run-time EDC is compared with a validation EDC associated with the retained file to identify a corruption of the retained file. The validation EDC is generated at an instance of placing the retained file in the retained FS. Furthermore, the validation EDC is based on at least one of entire content and metadata of the retained file. Based on the comparison, an original version of the retained file may is restored from a trusted backup system.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 10, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Arun Sankar, Jagadish Madhu, Ramesh Kannan Karuppasamy, Rajkumar Kannan
  • MAINTAINING FILES IN A RETAINED FILE SYSTEM
    Publication number: 20190196919
    Abstract: To maintain files in a retained file system, a run-time error detection code (EDC) is generated for a retained file. The run-time EDC is generated on the basis of at least one of entire content and metadata of the retained file. Further, the run-time EDC is compared with a validation EDC associated with the retained file to identify a corruption of the retained file. The validation EDC is generated at an instance of placing the retained file in the retained FS. Furthermore, the validation EDC is based on at least one of entire content and metadata of the retained file. Based on the comparison, an original version of the retained file may is restored from a trusted backup system.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 27, 2019
    Inventors: Arun Sankar, Jagadish Madhu, Ramesh Kannan Karuppasamy, Rajkumar Kannan
  • Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects
    Patent number: 10254642
    Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi
  • MODIFYING DESIGN LAYER OF INTEGRATED CIRCUIT (IC)
    Publication number: 20180180989
    Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 28, 2018
    Inventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi
  • Modifying design layer of integrated circuit (IC)
    Patent number: 9977325
    Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 22, 2018
    Assignee: International Business Machines Corporation
    Inventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi
  • MAINTAINING FILES IN A RETAINED FILE SYSTEM
    Publication number: 20170220426
    Abstract: To maintain files in a retained file system, a run-time error detection code (EDC) is generated for a retained file. The run-time EDC is generated on the basis of at least one of entire content and metadata of the retained file. Further, the run-time EDC is compared with a validation EDC associated with the retained file to identify a corruption of the retained file. The validation EDC is generated at an instance of placing the retained file in the retained FS. Furthermore, the validation EDC is based on at least one of entire content and metadata of the retained file. Based on the comparison, an original version of the retained file may is restored from a trusted backup system.
    Type: Application
    Filed: October 7, 2014
    Publication date: August 3, 2017
    Inventors: Arun Sankar, Jagadish Madhu, Ramesh Kannan K, Rajkumar Kannan
  • MODIFYING DESIGN LAYER OF INTEGRATED CIRCUIT (IC)
    Publication number: 20170108769
    Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Veeresh V. Deshpande, Howard S. Landis, Arun Sankar Mampazhy, Neelima Mandloi