Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: Adaptive decoder-drive encoder reconfiguration techniques are described. In one example, techniques include detecting an operational condition at a consumer using a sensor, the consumer receiving a communication of digital content from an encoder; generating an adaptation instruction by the decoder based on the detecting; transmitting the adaptation instruction by the decoder for receipt by the encoder; and receiving an adapted communication of the digital content generated by the encoder, the adapted communication caused by reconfiguration of the encoder based on the adaptation instruction received from the decoder.

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: Various codecs and methods of using the same are disclosed. In one aspect, a method of processing video data is provided that includes encoding or decoding the video data with a codec in aggressive deployment and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re-decoding the video data in a non-aggressive deployment or generating a skip picture.

Abstract: A native edge-triggered master-slave flip-flop exploits native latch topologies to create an edge-triggered master-slave flip-flop using a single clock phase having substantially reduced clock power consumption and substantially improved hold timing margin as compared to the clock power consumption and hold timing margin of a conventional master-slave flip-flop and other low power flip-flops.

Abstract: Various codecs and methods of using the same are disclosed. In one aspect, a method of processing video data is provided that includes encoding or decoding the video data with a codec in aggressive deployment and correcting one or more errors in the encoding or decoding wherein the error correction includes re-encoding or re-decoding the video data in a non-aggressive deployment or generating a skip picture.

Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

Abstract: An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.

Abstract: An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements.

Abstract: A latch or flip flop circuit with an increased operating frequency is disclosed. In particular, the operating frequency of the latch is increased by reducing the set up time of the latch circuit. A regenerative circuit is provided between the transmission gate of the latch circuit and the data output. The regenerative circuit comprises a pull up circuit and a pull down circuit. The circuit arrangement of the present invention may be applied to flip flop or latch circuits in combination with other flip flop or latch circuits such as a Master-Slave configuration.