Patents by Inventor Arun Thandapani
Arun Thandapani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230205627Abstract: A data storage device includes a non-volatile memory and a data storage controller. The data storage controller is configured to generate first XOR parities based on first data of a first metablock of the non-volatile memory and store the first XOR parities in a second metablock of the non-volatile memory. The data storage controller is also configured to generate second XOR parities corresponding to second data of the second metablock. The second data includes two or more XOR parities of the first XOR parities. The data storage controller is further configured to store the second parities in a reserved portion of the first metablock.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Varun Sharma, Vishal Sharma, Arun Thandapani
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Patent number: 11687409Abstract: A data storage device includes a non-volatile memory and a data storage controller. The data storage controller is configured to generate first XOR parities based on first data of a first metablock of the non-volatile memory and store the first XOR parities in a second metablock of the non-volatile memory. The data storage controller is also configured to generate second XOR parities corresponding to second data of the second metablock. The second data includes two or more XOR parities of the first XOR parities. The data storage controller is further configured to store the second parities in a reserved portion of the first metablock.Type: GrantFiled: December 28, 2021Date of Patent: June 27, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Varun Sharma, Vishal Sharma, Arun Thandapani
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Patent number: 11231883Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.Type: GrantFiled: July 2, 2020Date of Patent: January 25, 2022Assignee: Western Digital Technologies, Inc.Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M Gavens
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Publication number: 20220004336Abstract: A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Applicant: Western Digital Technologies, Inc.Inventors: Ankit Vijay Naghate, Rakshit Tikoo, Yogendra Singh Sikarwar, Ashish Singla, Arun Thandapani, Lee M. Gavens
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Patent number: 11036407Abstract: A storage system and method for smart folding are provided. In one example, the storage system has a memory with a plurality of single level cell (SLC) blocks and a multi-level cell (MLC) block. The MLC block has a plurality of pages, each with a different sense time. The storage system tracks a read count of each of the plurality of SLC blocks and determines how to fold the plurality of SLC blocks into the plurality of pages based on the read count of each of the plurality of SLC blocks and the sense time of each of the plurality of pages. In this way, SLC blocks with higher read counts can be folded into pages that have faster sense times.Type: GrantFiled: May 29, 2020Date of Patent: June 15, 2021Assignee: Western Digital Technologies, Inc.Inventors: Rakshit Tikoo, Ankit Naghate, Yogendra Singh Sikarwar, Arun Thandapani
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Patent number: 11036411Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.Type: GrantFiled: June 24, 2019Date of Patent: June 15, 2021Assignee: Western Digital Technologies, Inc.Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
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Publication number: 20200401332Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Applicant: Western Digital Technologies, Inc.Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
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Patent number: 10553301Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.Type: GrantFiled: August 15, 2017Date of Patent: February 4, 2020Assignee: SanDisk Technologies LLCInventors: Narayan K, Sateesh Desireddi, Aneesh Puthoor, Dharmaraju Marenahally Krishna, Arun Thandapani, Divya Prasad, Thendral Murugaiyan, Piyush Dhotre
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Patent number: 10535383Abstract: A die includes a plurality of memory cells. The die also includes a calculation circuit configured to determine a difference between a write temperature and a read temperature in response to a read request for user data stored in the memory cells. The die further includes a notification circuit configured to signal a cross-temperature condition in response to the difference satisfying a threshold.Type: GrantFiled: February 28, 2018Date of Patent: January 14, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Anantharaj Thalaimalaivanaraj, Suman Tenugu, Arun Thandapani, Dharmaraju Marenahally Krishna, Sainath Viswasarai
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Publication number: 20190267054Abstract: A die includes a plurality of memory cells. The die also includes a calculation circuit configured to determine a difference between a write temperature and a read temperature in response to a read request for user data stored in the memory cells. The die further includes a notification circuit configured to signal a cross-temperature condition in response to the difference satisfying a threshold.Type: ApplicationFiled: February 28, 2018Publication date: August 29, 2019Inventors: Anantharaj Thalaimalaivanaraj, Suman Tenugu, Arun Thandapani, Dharmaraju Marenahally Krishna, Sainath Viswasarai
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Patent number: 10319445Abstract: Apparatuses, systems, methods, and computer program products for programming an unprogrammed upper page based on lower page programming are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a data component that is configured to receive a write request for a first page of a set of multi-level storage cells of a non-volatile storage device. A set of multi-level storage cells includes a first page and a second page. A controller includes a page component that is configured to determine that a write request does not comprise data for at least a portion of a second page of a set of multi-level storage cells. A controller includes a write component that is configured to program at least a portion of a second page of a set of multi-level storage cells with data of a first page of a set of multi-level storage cells.Type: GrantFiled: November 30, 2017Date of Patent: June 11, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Bhavadip Solanki, Anantharaj Thalaimalai Vanaraj, Suman Tenugu, Arun Thandapani, Piyush Anil Dhotre, Chittoor Devarajan Sunilkumar, Dharmaraju Marenhally Krishna
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Publication number: 20190164612Abstract: Apparatuses, systems, methods, and computer program products for programming an unprogrammed upper page based on lower page programming are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a data component that is configured to receive a write request for a first page of a set of multi-level storage cells of a non-volatile storage device. A set of multi-level storage cells includes a first page and a second page. A controller includes a page component that is configured to determine that a write request does not comprise data for at least a portion of a second page of a set of multi-level storage cells. A controller includes a write component that is configured to program at least a portion of a second page of a set of multi-level storage cells with data of a first page of a set of multi-level storage cells.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Applicant: Western Digital Technologies, Inc.Inventors: BHAVADIP SOLANKI, ANANTHARAJ THALAIMALAI VANARAJ, SUMAN TENUGU, ARUN THANDAPANI, PIYUSH ANIL DHOTRE, CHITTOOR DEVARAJAN SUNILKUMAR, DHARMARAJU MARENHALLY KRISHNA
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Publication number: 20180350446Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.Type: ApplicationFiled: August 15, 2017Publication date: December 6, 2018Applicant: SanDisk Technologies LLCInventors: Narayan K, Sateesh Desireddi, Aneesh Puthoor, Dharmaraju Marenahally Krishna, Arun Thandapani, Divya Prasad, Thendral Murugaiyan, Piyush Dhotre
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Patent number: 10073627Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.Type: GrantFiled: January 13, 2016Date of Patent: September 11, 2018Assignee: SanDisk Technologies LLCInventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy, Arun Thandapani
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Patent number: 9691485Abstract: A storage system and method for marginal write-abort detection using a memory parameter change is provided. In one embodiment, a method for detecting a write abort is provided that is performed in a storage system having a memory. The method comprises reading a lower page in memory; determining if any data is written in the lower page; and in response to determining that no data is written in the lower page: increasing source voltage for memory cells in the lower page; re-reading the lower page; determining if a read failure exists in the re-read lower page; and in response to determining that a read failure exists in the re-read lower page, detecting a write abort. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: July 11, 2016Date of Patent: June 27, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Chittoor Devarajan Sunil Kumar, Divya Prasad, Piyush Anil Dhotre, Dharmaraju Marenahally Krishna, Thendral Murugaiyan, Arun Thandapani
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Publication number: 20160202910Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.Type: ApplicationFiled: January 13, 2016Publication date: July 14, 2016Applicant: SanDisk Technologies Inc.Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy, Arun Thandapani