Patents by Inventor Arun Upadhyaya Kishan

Arun Upadhyaya Kishan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11379195
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 5, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Henry Morgan, Ten Tzen, Christopher Martin McKinsey, YongKang Zhu, Terry Mahaffey, Pedro Miguel Sequeira de Justo Teixeira, Arun Upadhyaya Kishan, Youssef M. Barakat
  • Publication number: 20220027159
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Darek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
  • Patent number: 11163575
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: November 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Darek Mihocka, Arun Upadhyaya Kishan, Pedro Miguel Sequeira De Justo Teixeira
  • Publication number: 20210089282
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Inventors: Henry MORGAN, Ten TZEN, Christopher Martin MCKINSEY, YongKang ZHU, Terry MAHAFFEY, Pedro Miguel Sequeira de Justo TEIXEIRA, Arun Upadhyaya KISHAN, Youssef M. BARAKAT
  • Patent number: 10884720
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 5, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Henry Morgan, Ten Tzen, Christopher Martin McKinsey, YongKang Zhu, Terry Mahaffey, Pedro Miguel Sequeira de Justo Teixeira, Arun Upadhyaya Kishan, Youssef M. Barakat
  • Publication number: 20200319888
    Abstract: Unaligned atomic memory operations on a processor using a load-store instruction set architecture (ISA) that requires aligned accesses are performed by widening the memory access to an aligned address by the next larger power of two (e.g., 4-byte access is widened to 8 bytes, and 8-byte access is widened to 16 bytes). Data processing operations supported by the load-store ISA including shift, rotate, and bitfield manipulation are utilized to modify only the bytes in the original unaligned address so that the atomic memory operations are aligned to the widened access address. The aligned atomic memory operations using the widened accesses avoid the faulting exceptions associated with unaligned access for most 4-byte and 8-byte accesses. Exception handling is performed in cases in which memory access spans a 16-byte boundary.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Darek MIHOCKA, Arun Upadhyaya KISHAN, Pedro Miguel SEQUEIRA DE JUSTO TEIXEIRA
  • Patent number: 10621342
    Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kenneth D. Johnson, Sai Ganesh Ramachandran, Xin David Zhang, Arun Upadhyaya Kishan, David Alan Hepkin
  • Publication number: 20200110587
    Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Henry MORGAN, Ten TZEN, Christopher Martin MCKINSEY, YongKang ZHU, Terry MAHAFFEY, Pedro Miguel Sequeira de Justo TEIXEIRA, Arun Upadhyaya KISHAN, Youssef M. BARAKAT
  • Patent number: 10606653
    Abstract: A priority-based scheduling and execution of threads may enable the completion of higher-priority tasks above lower-priority tasks. Occasionally, a high-priority thread may request a resource that has already been reserved by a low-priority thread, and the higher-priority thread may be blocked until the low-priority thread relinquishes the reservation. Such prioritization may be acceptable if the low-priority thread is able to execute comparatively unimpeded, but in some scenarios, the low-priority thread may execute at a lower priority than a medium-priority thread that also has a lower priority than the high-priority thread. In this scenario, the medium-priority thread is effectively but incorrectly prioritized above the high-priority thread.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 31, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Arun Upadhyaya Kishan, Neill Michael Clift, Mehmet Iyigun, Yevgeniy Bak, Syed Aunn Hasan Raza
  • Patent number: 10552131
    Abstract: Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Clarence Siu Yeen Dang, Arun Upadhyaya Kishan
  • Publication number: 20190130102
    Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 2, 2019
    Inventors: Kenneth D. JOHNSON, Sai Ganesh RAMACHANDRAN, Xin David ZHANG, Arun Upadhyaya KISHAN, David Alan HEPKIN
  • Publication number: 20190114173
    Abstract: Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 18, 2019
    Inventors: Clarence Siu Yeen DANG, Arun Upadhyaya KISHAN
  • Patent number: 9569260
    Abstract: A priority-based scheduling and execution of threads may enable the completion of higher-priority tasks above lower-priority tasks. Occasionally, a high-priority thread may request a resource that has already been reserved by a lower-priority thread, and the higher-priority thread may be blocked until the lower-priority thread relinquishes the reservation. Such prioritization may be acceptable if the lower-priority thread is able to execute comparatively unimpeded, but in some scenarios, the lower-priority thread may execute at a lower priority than a third thread that also has a lower priority than the high-priority thread. In this scenario, the third thread is effectively but incorrectly prioritized above the high-priority thread.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: February 14, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Arun Upadhyaya Kishan, Neill Michael Clift, Mehmet Iyigun, Yevgeniy Bak, Syed Aunn Hasan Raza
  • Patent number: 9189605
    Abstract: A method of establishing a protected environment within a computing device including validating a kernel component loaded into a kernel of the computing device, establishing a security state for the kernel based on the validation, creating a secure process and loading a software component into the secure process, periodically checking the security state of the kernel, and notifying the secure process when the security state of the kernel has changed.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: November 17, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sumedh N. Barde, Jonathan D. Schwartz, Reid Joseph Kuhn, Alexandre Vicktorovich Grigorovitch, Kirt A. Debique, Chadd B. Knowlton, James M. Alkove, Geoffrey T. Dunbar, Michael J. Grier, Ming Ma, Chaitanya D. Upadhyay, Adil Ahmed Sherwani, Arun Upadhyaya Kishan
  • Publication number: 20140373027
    Abstract: One or more techniques and/or systems are provided for facilitating lifetime management of dynamically created child applications and/or for managing dependencies between a set of applications of an application package. In an example, a parent application may dynamically create a child application. A child lifetime of the child application may be managed independently and/or individually from lifetimes of other applications with which the child application does not have a dependency relationship. In another example, an application within an application package may be identified as a dependency application that may provide functionality depended upon by another application, such as a first application, within the application package. A dependency lifetime of the dependency application may be managed according to a first lifetime of the first application. In this way, lifetimes (e.g., initialization, execution, suspension, termination, etc.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Hari Pulapaka, Arun Upadhyaya Kishan, Pedro Miguel Teixeira, Alex Bendetov, Yaou Wei, Michael Hans Krause
  • Publication number: 20140359632
    Abstract: A priority-based scheduling and execution of threads may enable the completion of higher-priority tasks above lower-priority tasks. Occasionally, a high-priority thread may request a resource that has already been reserved by a lower-priority thread, and the higher-priority thread may be blocked until the lower-priority thread relinquishes the reservation. Such prioritization may be acceptable if the lower-priority thread is able to execute comparatively unimpeded, but in some scenarios, the lower-priority thread may execute at a lower priority than a third thread that also has a lower priority than the high-priority thread. In this scenario, the third thread is effectively but incorrectly prioritized above the high-priority thread.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Arun Upadhyaya Kishan, Neill Michael Clift, Mehmet Iyigun, Yevgeniy Bak, Syed Aunn Hasan Raza
  • Publication number: 20090158036
    Abstract: A method of establishing a protected environment within a computing device including validating a kernel component loaded into a kernel of the computing device, establishing a security state for the kernel based on the validation, creating a secure process and loading a software component into the secure process, periodically checking the security state of the kernel, and notifying the secure process when the security state of the kernel has changed.
    Type: Application
    Filed: February 23, 2009
    Publication date: June 18, 2009
    Applicant: Microsoft Corporation
    Inventors: Sumedh N. Barde, Jonathan D. Schwartz, Reid Joseph Kuhn, Alexandre Vicktorovich Grigorovitch, Kirt A. Debique, Chabd B. Knowlton, James M. Alkove, Geoffery T. Dunbar, Michael J. Grier, Ming Ma, Chaitanya D. Upadhyay, Adil Ahmed Sherwani, Arun Upadhyaya Kishan