Patents by Inventor Arun Vishwanathan
Arun Vishwanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10574748Abstract: This technology relates to a device, method, and non-transitory computer readable medium for allocating one or more resources optimally in a composite cloud environment. This technology involves configuring organization and service level quota values, describing service composition, service unit, service level agreement, defining allocation model and resource allocation optimization algorithm. Based on these predefined rules the infrastructure, software and manual resources are assigned, future allocation is forecasted and resources are allocated to complete the service requests received from the users.Type: GrantFiled: March 14, 2014Date of Patent: February 25, 2020Assignee: Infosys LimitedInventors: Shyam Kumar Doddavula, Mudit Kaushik, Arun Vishwanathan
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Publication number: 20140289412Abstract: This technology relates to a device, method, and non-transitory computer readable medium for allocating one or more resources optimally in a composite cloud environment. This technology involves configuring organization and service level quota values, describing service composition, service unit, service level agreement, defining allocation model and resource allocation optimization algorithm. Based on these predefined rules the infrastructure, software and manual resources are assigned, future allocation is forecasted and resources are allocated to complete the service requests received from the users.Type: ApplicationFiled: March 14, 2014Publication date: September 25, 2014Applicant: Infosys LimitedInventors: Shyam Kumar Doddavula, Mudit Kaushik, Arun Vishwanathan
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Patent number: 8727835Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: GrantFiled: September 23, 2013Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Publication number: 20140024297Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: ApplicationFiled: September 23, 2013Publication date: January 23, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Patent number: 8550878Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: GrantFiled: May 11, 2012Date of Patent: October 8, 2013Assignee: Micron Technology, Inc.Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Publication number: 20120225612Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: ApplicationFiled: May 11, 2012Publication date: September 6, 2012Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Patent number: 8192257Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: GrantFiled: April 6, 2006Date of Patent: June 5, 2012Assignee: Micron Technology, Inc.Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Publication number: 20070238297Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.Type: ApplicationFiled: April 6, 2006Publication date: October 11, 2007Applicant: Micron Technology, Inc.Inventors: Naga Chandrasekaran, Arun Vishwanathan
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Patent number: 6860802Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: GrantFiled: June 30, 2000Date of Patent: March 1, 2005Assignee: Rohm and Haas Electric Materials CMP Holdings, Inc.Inventors: Arun Vishwanathan, David B. James, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Publication number: 20050020082Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: ApplicationFiled: August 20, 2004Publication date: January 27, 2005Inventors: Arun Vishwanathan, David James, Lee Cook, Peter Burke, David Shidner
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Patent number: 6749485Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness and hydrolytic stability.Type: GrantFiled: September 20, 2000Date of Patent: June 15, 2004Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
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Patent number: 6736709Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing, pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad also exhibits a stable morphology that can be reproduced easily and consistently. The pad surface has macro-texture that includes perforations as well as surface groove designs The surface groove designs have specific relationships between groove depth and overall pad thickness and groove.area and land area.Type: GrantFiled: August 3, 2000Date of Patent: May 18, 2004Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
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Patent number: 6599542Abstract: A non-stick chewing gum base containing from about 2 to 25% of a plasticized proteinaceous material and a combination of gum base materials, absent elastomer solvent and wax, which render a chewing gun composition non-stick with respect to non-porous surfaces, such as denture materials, as well as common surfaces such as floors, and including porous surfaces such as carpets.Type: GrantFiled: August 11, 1998Date of Patent: July 29, 2003Assignee: Warner-Lambert CompanyInventors: Magdy Malak Abdel-Malik, Arun Vishwanathan, Angel Manuel Orama
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Patent number: 6582283Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: GrantFiled: July 11, 2002Date of Patent: June 24, 2003Assignee: Rodel Holdings, Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Publication number: 20030027500Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: ApplicationFiled: July 11, 2002Publication date: February 6, 2003Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Patent number: 6454634Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.Type: GrantFiled: August 3, 2000Date of Patent: September 24, 2002Assignee: Rodel Holdings Inc.Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
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Patent number: 6361409Abstract: A polishing pad made of polymeric material has an improved surface layer which is provided by treating a surface of the polishing pad with a chemical solvent. Solubility parameter is used to select a suitable chemical solvent. The treated polishing pad can be conditioned in substantially less time than an untreated pad.Type: GrantFiled: September 28, 1999Date of Patent: March 26, 2002Assignee: Rodel Holdings Inc.Inventors: Arun Vishwanathan, David L. Shidner
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Patent number: 5882702Abstract: Process for the formation of a plasticized proteinaceous material in which a plasticizer component is selectively matched with a protein component to form a blend. The blend is heated under controlled shear conditions to produce the plasticized proteinaceous material having the plasticizer component uniformly distributed within the protein component. The plasticized proteinaceous material is used for a variety of purposes including the production of gums and confectionery compositions.Type: GrantFiled: September 24, 1997Date of Patent: March 16, 1999Assignee: Warner-Lambert CompanyInventors: Magdy Malak Abdel-Malik, Nick Steve D'Ottavio, Vipul Bhupendra Dave, Arun Vishwanathan