Patents by Inventor Arun Vishwanathan

Arun Vishwanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10574748
    Abstract: This technology relates to a device, method, and non-transitory computer readable medium for allocating one or more resources optimally in a composite cloud environment. This technology involves configuring organization and service level quota values, describing service composition, service unit, service level agreement, defining allocation model and resource allocation optimization algorithm. Based on these predefined rules the infrastructure, software and manual resources are assigned, future allocation is forecasted and resources are allocated to complete the service requests received from the users.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 25, 2020
    Assignee: Infosys Limited
    Inventors: Shyam Kumar Doddavula, Mudit Kaushik, Arun Vishwanathan
  • Publication number: 20140289412
    Abstract: This technology relates to a device, method, and non-transitory computer readable medium for allocating one or more resources optimally in a composite cloud environment. This technology involves configuring organization and service level quota values, describing service composition, service unit, service level agreement, defining allocation model and resource allocation optimization algorithm. Based on these predefined rules the infrastructure, software and manual resources are assigned, future allocation is forecasted and resources are allocated to complete the service requests received from the users.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 25, 2014
    Applicant: Infosys Limited
    Inventors: Shyam Kumar Doddavula, Mudit Kaushik, Arun Vishwanathan
  • Patent number: 8727835
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20140024297
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Patent number: 8550878
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20120225612
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: May 11, 2012
    Publication date: September 6, 2012
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Patent number: 8192257
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Publication number: 20070238297
    Abstract: Processing pads for mechanical and/or chemical-mechanical planarization or polishing of substrates in the fabrication of microelectronic devices, methods for making the pads, and methods, apparatus, and systems that utilize and incorporate the processing pads are provided. The processing pads include grooves or other openings in the abrading surface containing a solid or partially solid fill material that can be selectively removed as desired to maintain the fill at an about constant or set distance from the abrading surface of the pad and an about constant depth of the pad openings for multiple processing and conditioning applications over the life of the pad.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 11, 2007
    Applicant: Micron Technology, Inc.
    Inventors: Naga Chandrasekaran, Arun Vishwanathan
  • Patent number: 6860802
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: March 1, 2005
    Assignee: Rohm and Haas Electric Materials CMP Holdings, Inc.
    Inventors: Arun Vishwanathan, David B. James, Lee Melbourne Cook, Peter A. Burke, David Shidner
  • Publication number: 20050020082
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.
    Type: Application
    Filed: August 20, 2004
    Publication date: January 27, 2005
    Inventors: Arun Vishwanathan, David James, Lee Cook, Peter Burke, David Shidner
  • Patent number: 6749485
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness and hydrolytic stability.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: June 15, 2004
    Assignee: Rodel Holdings, Inc.
    Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
  • Patent number: 6736709
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing, pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad also exhibits a stable morphology that can be reproduced easily and consistently. The pad surface has macro-texture that includes perforations as well as surface groove designs The surface groove designs have specific relationships between groove depth and overall pad thickness and groove.area and land area.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: May 18, 2004
    Assignee: Rodel Holdings, Inc.
    Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner, Joseph K. So, John V. H. Roberts
  • Patent number: 6599542
    Abstract: A non-stick chewing gum base containing from about 2 to 25% of a plasticized proteinaceous material and a combination of gum base materials, absent elastomer solvent and wax, which render a chewing gun composition non-stick with respect to non-porous surfaces, such as denture materials, as well as common surfaces such as floors, and including porous surfaces such as carpets.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: July 29, 2003
    Assignee: Warner-Lambert Company
    Inventors: Magdy Malak Abdel-Malik, Arun Vishwanathan, Angel Manuel Orama
  • Patent number: 6582283
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 24, 2003
    Assignee: Rodel Holdings, Inc.
    Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
  • Publication number: 20030027500
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.
    Type: Application
    Filed: July 11, 2002
    Publication date: February 6, 2003
    Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
  • Patent number: 6454634
    Abstract: An improved pad and process for polishing metal damascene structures on a semiconductor wafer. The process includes the steps of pressing the wafer against the surface of a polymer sheet in combination with an aqueous-based liquid that optionally contains sub-micron particles and providing a means for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer, wherein the polishing pad has a low elastic recovery when said load is removed, so that the mechanical response of the sheet is largely anelastic. The improved pad is characterized by a high energy dissipation coupled with a high pad stiffness. The pad exhibits a stable morphology that can be reproduced easily and consistently. The pad surface resists glazing, thereby requiring less frequent and less aggressive conditioning.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: September 24, 2002
    Assignee: Rodel Holdings Inc.
    Inventors: David B. James, Arun Vishwanathan, Lee Melbourne Cook, Peter A. Burke, David Shidner
  • Patent number: 6361409
    Abstract: A polishing pad made of polymeric material has an improved surface layer which is provided by treating a surface of the polishing pad with a chemical solvent. Solubility parameter is used to select a suitable chemical solvent. The treated polishing pad can be conditioned in substantially less time than an untreated pad.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: March 26, 2002
    Assignee: Rodel Holdings Inc.
    Inventors: Arun Vishwanathan, David L. Shidner
  • Patent number: 5882702
    Abstract: Process for the formation of a plasticized proteinaceous material in which a plasticizer component is selectively matched with a protein component to form a blend. The blend is heated under controlled shear conditions to produce the plasticized proteinaceous material having the plasticizer component uniformly distributed within the protein component. The plasticized proteinaceous material is used for a variety of purposes including the production of gums and confectionery compositions.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: March 16, 1999
    Assignee: Warner-Lambert Company
    Inventors: Magdy Malak Abdel-Malik, Nick Steve D'Ottavio, Vipul Bhupendra Dave, Arun Vishwanathan