Abstract: An RFID transceiver (200) includes a common frequency source (250), a receiving channel (230) and a transmitting channel (240). The common frequency source (250) is configured to provide a predefined intermediate frequency signal fIF, and a predefined carrier frequency signal fc. The RFID receiving channel (230) includes an upconverting mixer (232) having a first input coupled to receive the predefined intermediate frequency signal fIF, a second input coupled to receive the predefined carrier frequency signal fc, and an output, the upconverting mixer (232) operable to produce an upconverted signal at a frequency defined by fc±fIF.

Abstract: An RFID transceiver (200) includes a common frequency source (50), a receiving channel (230) and a transmitting channel (240). The common frequency source (250) is configured to provide a predefined intermediate frequency signal fIF, and a predefined carrier frequency signal fc. The RFID receiving channel (230) includes an upconverting mixer (232) having a first input coupled to receive the predefined intermediate frequency signal fIF, a second input coupled to receive the predefined carrier frequency signal fc, and an output, the upconverting mixer (232) operable to produce an upconverted signal at a frequency defined by fc±fIF.

Abstract: A clock and data recovery (CDR) circuit comprises a phase detector (PD) and a quadrature phase (QP) detector. A frequency detector (FD) is coupled to the PD and QP detector. The FD detects frequency difference between the output signals of the PD and QP detector and provides an FD output signal. A summer is coupled to the PD and FD for summing the PD and FD output signals, and for providing a summer output signal. The CDR further comprises a voltage-controlled oscillator (VCO) for receiving a direct current signal and providing a recovered clock signal. A polyphase filter is coupled to each of the VCO, PD, and QP detector. A re-timer is coupled to the polyphase filter and provides a re-timed data signal, wherein the CDR circuit is on-chip and the polyphase filter converts clock signals into phase reference signals.

Abstract: A variable high frequency voltage controlled oscillator (VCO) which is fully integrated. By controlling, with a control voltage, the collector current flowing through one transistor of the integrated oscillator circuit, the diffusion capacitance (also known as base-charging capacitance) of that transistor is varied. Since, in conjunction with an inductance, this capacitance to a large degree determines the frequency of oscillation of the integrated circuit, a fully integrated VCO is made possible.

Abstract: A multiple frequency shifting oscillator that will provide a plurality of frequencies dependent upon a contents of an input shifting signal an input shifting signal is disclosed. The multiple frequency shifting oscillator has an amplifier with first input, a second input, which is coupled to a ground reference potential and an output. The multiple frequency shifting oscillator has a first impedance that is coupled between the first input of the amplifier and the ground reference potential, a second impedance that is coupled between the output of the amplifier and the ground reference potential, and a third impedance coupled between the output and the input of the amplifier. The multiple frequency shifting oscillator has a plurality of frequency shifting impedances that when selected will be coupled to the first impedance so as to shift the frequency of the multiple frequency shifting oscillator.