Patents by Inventor Aruna Govind

Aruna Govind has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6982610
    Abstract: An impedance adjustment system comprising current source, a first series and a second series connected string of predetermined number of resistors, a first and second switch network, a first, second and third logic circuit and a comparator. By applying the principles of the present invention, embodiments can be made in which variations in a Silicide block of resistors used to terminate a signal line are “tuned out” to get a more precise termination impedance. Embodiments may be made that hold the termination impedance substantially constant over time by continually adjusting in response to variations in process, temperature and supply voltage. IDDQ requirements can be met by latching, by double buffering, the outputs of comparators providing an encoded resistor network setting for the termination impedance, and then powering down the circuit. Embodiments of the present invention avoid the use of trims and fuses, thus reducing fabrication cost.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: January 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Aruna Govind
  • Publication number: 20050184824
    Abstract: An impedance adjustment system. A current source is adapted to provide a predetermined stabilized current corresponding to a current through a first resistor having across it a predetermined stabilized voltage, for example a bandgap voltage. A first series connected string of a first predetermined number of resistors is coupled between the current source and ground, being coupled to the current source at a sense node. A first switch network is adapted to select ones of the first predetermined number of resistors for inclusion in the first series connected string. A first logic circuit is adapted to control the first switch network to incrementally change the total resistance of the first series connected string. A comparator is provided, having a first input coupled to the predetermined stabilized voltage, having a second input coupled to the sense node, and having an output representing the direction of difference in voltage between the first input and the second input of the comparator.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 25, 2005
    Inventor: Aruna Govind