Abstract: Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic.

Abstract: Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic.

Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

Abstract: First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

Abstract: A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.

Abstract: A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.

Abstract: A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.

Abstract: A nonvolatile memory system includes a memory controller in communication with multiple memory dies through multiple memory interfaces. Multiple ECC blocks are provided to decode data from the multiple memory interfaces. ECC blocks are provided with a clock signal that may have a frequency that is lower than another clock signal that is provided to a host interface.