Patents by Inventor Arunachalam Vaidyanathan
Arunachalam Vaidyanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8331359Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.Type: GrantFiled: March 12, 2010Date of Patent: December 11, 2012Assignee: Juniper Networks, Inc.Inventors: Albert Weichung Kuo, Reuven Meyer Samuel, Debashis Basu, Arunachalam Vaidyanathan, Spencer Greene
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Publication number: 20100169608Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Applicant: JUNIPER NETWORKS, INC.Inventors: Albert Weichung KUO, Reuven Meyer SAMUEL, Debashis BASU, Arunachalam VAIDYANATHAN, Spencer GREENE
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Patent number: 7710952Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.Type: GrantFiled: November 20, 2007Date of Patent: May 4, 2010Assignee: Juniper Networks, Inc.Inventors: Albert Weichung Kuo, Reuven Meyer Samuel, Debashis Basu, Arunachalam Vaidyanathan, Spencer Greene
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Patent number: 7317718Abstract: A network device includes one or more processing units and an external memory. Each of the one or more processing units includes a centralized counter configured to perform accounting for the respective processing unit. The external memory is associated with at least one of the one or more processing units and is configured to store a group of count values for the at least one processing unit.Type: GrantFiled: December 6, 2002Date of Patent: January 8, 2008Assignee: Juniper Networks, Inc.Inventors: Albert Weichung Kuo, Reuven Meyer Samuel, Debashis Basu, Arunachalam Vaidyanathan, Spencer Greene
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Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
Patent number: 5905885Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.Type: GrantFiled: September 19, 1997Date of Patent: May 18, 1999Assignee: Cirrus Logic, Inc.Inventors: Bryan M. Richter, Stephen A. Smith, Daniel G. Bezzant, Kasturiraman Gopalaswamy, Suhas Anand Shetty, Arunachalam Vaidyanathan -
Patent number: 5812858Abstract: An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set.Type: GrantFiled: September 25, 1996Date of Patent: September 22, 1998Assignee: Cirrus Logic, Inc.Inventors: Narasimha R. Nookala, Ashutosh S. Dikshit, Daniel G. Bezzant, Stephen A. Smith, Jihad Y. Abudayyeh, Arunachalam Vaidyanathan
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Patent number: 5796981Abstract: An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit.Type: GrantFiled: September 16, 1994Date of Patent: August 18, 1998Assignee: Cirrus Logic, Inc.Inventors: Jihad Y. Abudayyeh, Ashutosh S. Dikshit, Daniel G. Bezzant, Stephen A. Smith, Narasimha R. Nookala, Arunachalam Vaidyanathan
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Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
Patent number: 5727184Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.Type: GrantFiled: June 27, 1994Date of Patent: March 10, 1998Assignee: Cirrus Logic, Inc.Inventors: Bryan M. Richter, Stephen A. Smith, Daniel G. Bezzant, Kasturiraman Gopalaswamy, Suhas Anand Shetty, Arunachalam Vaidyanathan -
Patent number: 5594874Abstract: An integrated automatic bus setting, sensing and switching interface unit is manufactured on board an integrated circuit to interface between the integrated circuit and the system bus. The interface unit can support a plurality of bus structures utilizing the same pins on the integrated circuit for different functions. Several modes of establishing an interface structure are available in the unit. An Address Strobe pin on the integrated circuit is used to automatically detect a signal level representative of the bus structure to be used. A code representative of the parameters of the bus structure is also stored in a configuration register for controlling the interface unit and configuring the pins on the integrated circuit for the specific bus structure to be used. The Basic Input Output System (BIOS) as its first operation stores the code in a register whose contents are then written to the configuration register of the integrated circuit for controlling and configuring the integrated circuit.Type: GrantFiled: September 30, 1993Date of Patent: January 14, 1997Assignee: Cirrus Logic, Inc.Inventors: Puducode S. Narayanan, Tai T. Nguyen, Arunachalam Vaidyanathan, Edward C. Garcia