Abstract: Embodiments herein maximize frame usage by selectively arranging the data within the frame thereby giving the transmitting processor additional time generate and transmit the data within the frame without increasing the time gap G of the frame and without increasing the overall length of the frame. Further, the selective arrangement also gives the receiving processor additional time to process the data of the frame and send Ack/Nack information regarding the success/failure of the processing without increasing the time gap G of the frame and without increasing the overall length of the frame. Other aspects, embodiments, and features are also claimed and described.

Abstract: Aspects provide techniques and apparatus for wireless communications (e.g., for saving power when performing control channel processing when in an idle mode or in a “PDCCH only” in connected mode). An exemplary method includes performing, using a processor, a first type of control channel processing in a first connection state using a firmware image stored in internal memory of the processor, wherein performing control channel processing comprises accessing memory external to the processor, determining one or more conditions for entering a low-power mode (LPM) associated with the processor are satisfied, entering the LPM based on the determination, wherein entering into the LPM includes at least one of disabling or disallowing access to the external memory based on entering the LPM, and performing, using the processor, a second type of control channel processing using the firmware image stored in internal memory of the processor based on entering the LPM.

Abstract: Aspects provide techniques and apparatus for wireless communications (e.g., for saving power when performing control channel processing when in an idle mode or in a “PDCCH only” in connected mode). An exemplary method includes performing, using a processor, a first type of control channel processing in a first connection state using a firmware image stored in internal memory of the processor, wherein performing control channel processing comprises accessing memory external to the processor, determining one or more conditions for entering a low-power mode (LPM) associated with the processor are satisfied, entering the LPM based on the determination, wherein entering into the LPM includes at least one of disabling or disallowing access to the external memory based on entering the LPM, and performing, using the processor, a second type of control channel processing using the firmware image stored in internal memory of the processor based on entering the LPM.

Abstract: Embodiments herein maximize frame usage by selectively arranging the data within the frame thereby giving the transmitting processor additional time generate and transmit the data within the frame without increasing the time gap G of the frame and without increasing the overall length of the frame. Further, the selective arrangement also gives the receiving processor additional time to process the data of the frame and send Ack/Nack information regarding the success/failure of the processing without increasing the time gap G of the frame and without increasing the overall length of the frame. Other aspects, embodiments, and features are also claimed and described.

Abstract: A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.

Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.

Abstract: A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Abstract: An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

Abstract: Methods and apparatus for resolving frequency errors in a wireless device transitioning from a first communication network to a second communication network are disclosed. The methods and apparatus effect reception of a first and second channels from the second communication network where the first channel has known characteristics. The first channel is then decoding for a prescribed period and an initial frequency error value is determined based on the decoding of the first channel. A digital frequency rotator is then adjusted based on the initial frequency error value for purposes of decoding the second channel. The second channel is then decoded using the digital frequency rotator as adjusted based on the initial frequency error value, without further calculation of the frequency error.

Abstract: Techniques for scheduling measurements for cells in multiple (e.g., GSM and W-CDMA) wireless communication systems are described. GSM neighbor cells are categorized based on a number of states. The states are prioritized in a manner to achieve good performance. The GSM neighbor cells are thus assigned different priorities depending on their states. W-CDMA neighbor cells are prioritized relative to the states for GSM cells. All W-CDMA neighbor cells can be assigned the same state, given the same priority, and considered as “one” W-CDMA cell in the scheduling. A cell in the GSM or W-CDMA system is selected based on the priorities of the neighbor cells, and the selected cell is scheduled for measurement in the next available frame. The highest-ranking GSM or W-CDMA cell for each idle frame is thus granted use of that idle frame for measurement.

Abstract: A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

Abstract: Within a receiver, a channel estimation mechanism involves a hardware interpolator. In a first mode, narrowband pilot values are analyzed to generate channel parameters that are supplied to the interpolator such that the interpolator generates channel estimate values. The channel estimate values are used to demodulate a tile of a frame. In a second mode, broadband pilot values are supplied to an IFFT, thereby generating time domain values. After time domain processing, an FFT is employed to generate intermediate channel estimate values. These intermediate values are analyzed to determine channel parameters, which in turn are supplied to the hardware interpolator so that the interpolator generates a larger number of channel estimate values. After phase adjustment, the channel estimate values are used in demodulation. Use of the interpolator in the broadband mode allows the FFT employed to be of a smaller order, and to consume less power and/or processing resources.

Abstract: An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

Abstract: A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Abstract: A method for sending an acknowledgment message in a wireless communication system is disclosed. A first signal is received before receiving a second signal from a transmitter. Decoded first data is extracted from the first signal. A third signal is produced by encoding and modulating the decoded first data. The second signal is demodulated to produce second symbols. The third signal and the second symbols are correlated.

Abstract: A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.