Patents by Inventor Arunava Saha

Arunava Saha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117532
    Abstract: The system obtains a hierarchy representing a construction site, where the hierarchy includes a parent node and a child node, and obtains a first computer model of a first construction site including a first multiplicity of virtual objects. Based on the hierarchy representing the construction site, and the first computer model of the first construction site, the system creates a first map between the hierarchy representing the construction site and the first computer model of the first construction site. The system trains an artificial intelligence based on the first map, and then provides to the artificial intelligence a second computer model of a second construction site. The system receives from the artificial intelligence a second map between the hierarchy representing the construction site and the second computer model.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 10, 2025
    Inventors: John Stalbaum, Richard Will Turner, Arunava Saha, Marin Lukovic, Michael Grinshpon, Rohit Srikonda, Abhishek Singh
  • Publication number: 20250117706
    Abstract: The system obtains a hierarchy representing a construction site, and multiple queries associated with a node in the hierarchy, where a query among the multiple queries requests an indication of a stage of construction associated with an object at the construction site represented by the node, and where the query among the multiple queries requests an answer from a binary set. The system obtains a recording of the object at the construction site and presents the recording and the multiple queries to a user. The system receives the answer from the binary set from the user, and creates an artificial intelligence training dataset based on the answer associated with the binary set and the recording of the object.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 10, 2025
    Inventors: John Stalbaum, Richard Will Turner, Arunava Saha, Marin Lukovic, Michael Grinshpon, Rohit Srikonda, Abhishek Singh
  • Publication number: 20250118020
    Abstract: The system obtains a floor plan associated with a construction site, and a three-dimensional computer model of the construction site, a trajectory through the construction site, and a recording of the construction site. The system establishes a correspondence between the trajectory and the floor plan. Based on the correspondence between the trajectory and the floor plan, the system creates a virtual camera associated with the three-dimensional computer model and a virtual trajectory, where the virtual trajectory influences virtual objects visible to the virtual camera, and the virtual objects visible to the virtual camera match objects visible to a camera making the recording. The system determines a transformation of the camera between an initial image and a subsequent image in the recording, and applies the transformation to the virtual camera to obtain a virtual trajectory of the virtual camera associated with the three-dimensional computer model.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 10, 2025
    Inventors: John Stalbaum, Richard Will Turner, Arunava Saha, Marin Lukovic, Michael Grinshpon, Rohit Srikonda, Abhishek Singh
  • Publication number: 20250116527
    Abstract: The system obtains a first recording of a construction site captured at a first time, and a first virtual trajectory of a first virtual camera, and creates a first data structure representing the first recording. The system obtains a second recording of the construction site captured at a second time, and creates a second data structure representing the second recording. The system establishes a correspondence between the first and second data structures by creating a map between a second image in the second recording and a first image in the first recording by efficiently searching the first data structure for the first image similar to the second image. The system obtains a first location of the first virtual camera corresponding to the first image and, based on the map between the first and second image, determines a second location of a second virtual camera corresponding to the second image.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 10, 2025
    Inventors: John Stalbaum, Richard Will Turner, Arunava Saha, Marin Lukovic, Michael Grinshpon, Rohit Srikonda, Abhishek Singh
  • Patent number: 12254429
    Abstract: Systems and methods for evaluating construction of structures are disclosed. Building information modeling (BIM) data is received in a non-standardized format for a set of structures undergoing construction. Scheduling data is received associated with construction of each structure in the set of structures. A database is accessed that stores construction data that associates multiple elements of construction projects in a hierarchical configuration. Using the BIM data and the scheduling data, a model is generated that standardizes how particular elements of a particular structure relate to the multiple elements in the hierarchical configuration. Using the generated model, a status of construction of the particular structure is generated. In some implementations, the model is generated and/or trained using machine learning.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 18, 2025
    Assignee: Doxel, Inc.
    Inventors: Arunava Saha, Dobromir Voyager Montauk, Richard William Turner, Matthew Paul Orban
  • Publication number: 20220383231
    Abstract: Systems and methods for evaluating construction of structures are disclosed. Building information modeling (BIM) data is received in a non-standardized format for a set of structures undergoing construction. Scheduling data is received associated with construction of each structure in the set of structures. A database is accessed that stores construction data that associates multiple elements of construction projects in a hierarchical configuration. Using the BIM data and the scheduling data, a model is generated that standardizes how particular elements of a particular structure relate to the multiple elements in the hierarchical configuration. Using the generated model, a status of construction of the particular structure is generated. In some implementations, the model is generated and/or trained using machine learning.
    Type: Application
    Filed: May 31, 2022
    Publication date: December 1, 2022
    Inventors: Arunava Saha, Dobromir Voyager Montauk, Richard William Turner, Matthew Paul Orban
  • Patent number: 11501048
    Abstract: A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties—i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 15, 2022
    Assignee: Synopsys, Inc.
    Inventors: Arunava Saha, Chuan Jiang, Manish Pandey
  • Patent number: 11010522
    Abstract: In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This interface allows the user to interactively select the FPV properties and/or the faults to be used for fault analysis. The user interface may provide a view of the faults, for example by listing faults or summarizing faults by class, type, etc.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 18, 2021
    Assignee: Synopsys, Inc.
    Inventors: Xiaolin Chen, Arunava Saha, Sandeep Jana, Pratik Mahajan, Jinnan Huang
  • Patent number: 10592624
    Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 17, 2020
    Assignee: Synopsis, Inc.
    Inventors: Sandeep Jana, Arunava Saha, Pratik Mahajan, Per Bjesse, Alfred Koelbl
  • Patent number: 10521536
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 31, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha
  • Patent number: 10503853
    Abstract: A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Synopsys, Inc.
    Inventors: Arunava Saha, Himanshu Jain, Manish Pandey, Ashvin Dsouza, Per Mattias Bjesse
  • Publication number: 20190147121
    Abstract: In one aspect, a fault injection environment and a formal property verification environment are combined in a single integrated flow that allows the user to go back and forth between the two tasks. A system that unifies formal property verification and fault injection includes user interfaces that support the unified use model. In one approach, the FPV tool is the master and its user interface is the primary interface for the user to set up, run and debug faults as well as checkers. This interface allows the user to interactively select the FPV properties and/or the faults to be used for fault analysis. The user interface may provide a view of the faults, for example by listing faults or summarizing faults by class, type, etc.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 16, 2019
    Inventors: Xiaolin Chen, Arunava Saha, Sandeep Jana, Pratik Mahajan, Jinnan Huang
  • Publication number: 20180349521
    Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on the injected faults and the existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 6, 2018
    Inventors: Sandeep Jana, Arunava Saha, Pratik Mahajan, Per Bjesse, Alfred Koelbl
  • Publication number: 20180144071
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, and running a machine-learning algorithm for hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method of apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha